Lines Matching defs:Op1
386 unsigned Op1 = getRegForValue(I->getOperand(1));
387 if (Op1 == 0) return false;
391 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
447 unsigned Op1 = getRegForValue(I->getOperand(1));
448 if (Op1 == 0)
458 Op1, Op1IsKill);
1117 unsigned /*Op1*/, bool /*Op1IsKill*/) {
1147 unsigned /*Op1*/, bool /*Op1IsKill*/,
1227 unsigned Op1, bool Op1IsKill) {
1234 .addReg(Op1, Op1IsKill * RegState::Kill);
1238 .addReg(Op1, Op1IsKill * RegState::Kill);
1248 unsigned Op1, bool Op1IsKill,
1256 .addReg(Op1, Op1IsKill * RegState::Kill)
1261 .addReg(Op1, Op1IsKill * RegState::Kill)
1337 unsigned Op1, bool Op1IsKill,
1345 .addReg(Op1, Op1IsKill * RegState::Kill)
1350 .addReg(Op1, Op1IsKill * RegState::Kill)
1361 unsigned Op1, bool Op1IsKill,
1369 .addReg(Op1, Op1IsKill * RegState::Kill)
1374 .addReg(Op1, Op1IsKill * RegState::Kill)
