Lines Matching refs:ISD
49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
67 case ISD::ANY_EXTEND:
68 case ISD::CTLZ:
69 case ISD::CTPOP:
70 case ISD::CTTZ:
71 case ISD::FABS:
72 case ISD::FCEIL:
73 case ISD::FCOS:
74 case ISD::FEXP:
75 case ISD::FEXP2:
76 case ISD::FFLOOR:
77 case ISD::FLOG:
78 case ISD::FLOG10:
79 case ISD::FLOG2:
80 case ISD::FNEARBYINT:
81 case ISD::FNEG:
82 case ISD::FP_EXTEND:
83 case ISD::FP_TO_SINT:
84 case ISD::FP_TO_UINT:
85 case ISD::FRINT:
86 case ISD::FSIN:
87 case ISD::FSQRT:
88 case ISD::FTRUNC:
89 case ISD::SIGN_EXTEND:
90 case ISD::SINT_TO_FP:
91 case ISD::TRUNCATE:
92 case ISD::UINT_TO_FP:
93 case ISD::ZERO_EXTEND:
97 case ISD::ADD:
98 case ISD::AND:
99 case ISD::FADD:
100 case ISD::FDIV:
101 case ISD::FMUL:
102 case ISD::FPOW:
103 case ISD::FREM:
104 case ISD::FSUB:
105 case ISD::MUL:
106 case ISD::OR:
107 case ISD::SDIV:
108 case ISD::SREM:
109 case ISD::SUB:
110 case ISD::UDIV:
111 case ISD::UREM:
112 case ISD::XOR:
113 case ISD::SHL:
114 case ISD::SRA:
115 case ISD::SRL:
118 case ISD::FMA:
151 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
161 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
177 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
185 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(),
191 return DAG.getNode(ISD::FPOWI, N->getDebugLoc(),
202 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
209 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
247 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
265 Cond = DAG.getNode(ISD::AND, N->getDebugLoc(), CondVT,
272 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), CondVT,
277 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
284 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
291 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), LHS.getValueType(),
309 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
319 if (Arg.getOpcode() == ISD::UNDEF)
336 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
340 ISD::NodeType ExtendCode =
365 case ISD::BITCAST:
368 case ISD::ANY_EXTEND:
369 case ISD::ZERO_EXTEND:
370 case ISD::SIGN_EXTEND:
373 case ISD::CONCAT_VECTORS:
376 case ISD::EXTRACT_VECTOR_ELT:
379 case ISD::STORE:
404 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
419 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
429 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0),
439 Res = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0),
495 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
496 case ISD::VSELECT:
497 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
498 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
499 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
500 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
501 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
502 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
503 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
504 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
505 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
506 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
507 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
508 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
509 case ISD::LOAD:
512 case ISD::SETCC:
515 case ISD::VECTOR_SHUFFLE:
519 case ISD::ANY_EXTEND:
520 case ISD::CONVERT_RNDSAT:
521 case ISD::CTLZ:
522 case ISD::CTTZ:
523 case ISD::CTLZ_ZERO_UNDEF:
524 case ISD::CTTZ_ZERO_UNDEF:
525 case ISD::CTPOP:
526 case ISD::FABS:
527 case ISD::FCEIL:
528 case ISD::FCOS:
529 case ISD::FEXP:
530 case ISD::FEXP2:
531 case ISD::FFLOOR:
532 case ISD::FLOG:
533 case ISD::FLOG10:
534 case ISD::FLOG2:
535 case ISD::FNEARBYINT:
536 case ISD::FNEG:
537 case ISD::FP_EXTEND:
538 case ISD::FP_ROUND:
539 case ISD::FP_TO_SINT:
540 case ISD::FP_TO_UINT:
541 case ISD::FRINT:
542 case ISD::FSIN:
543 case ISD::FSQRT:
544 case ISD::FTRUNC:
545 case ISD::SIGN_EXTEND:
546 case ISD::SINT_TO_FP:
547 case ISD::TRUNCATE:
548 case ISD::UINT_TO_FP:
549 case ISD::ZERO_EXTEND:
553 case ISD::ADD:
554 case ISD::SUB:
555 case ISD::MUL:
556 case ISD::FADD:
557 case ISD::FSUB:
558 case ISD::FMUL:
559 case ISD::SDIV:
560 case ISD::UDIV:
561 case ISD::FDIV:
562 case ISD::FPOW:
563 case ISD::AND:
564 case ISD::OR:
565 case ISD::XOR:
566 case ISD::SHL:
567 case ISD::SRA:
568 case ISD::SRL:
569 case ISD::UREM:
570 case ISD::SREM:
571 case ISD::FREM:
574 case ISD::FMA:
640 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
641 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
649 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
650 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
664 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
665 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
675 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size());
678 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size());
696 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size());
699 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size());
711 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
713 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
721 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
722 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
752 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
755 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
782 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
795 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
801 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
806 ISD::LoadExtType ExtType = LD->getExtensionType();
819 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
824 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
826 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
832 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
854 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
856 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
859 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
861 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1),
883 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
885 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
889 if (N->getOpcode() == ISD::FP_ROUND) {
892 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
899 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
996 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
1001 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size());
1044 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1045 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1046 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1047 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1048 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1049 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1050 case ISD::STORE:
1053 case ISD::VSELECT:
1056 case ISD::CTTZ:
1057 case ISD::CTLZ:
1058 case ISD::CTPOP:
1059 case ISD::FP_EXTEND:
1060 case ISD::FP_TO_SINT:
1061 case ISD::FP_TO_UINT:
1062 case ISD::SINT_TO_FP:
1063 case ISD::UINT_TO_FP:
1064 case ISD::FTRUNC:
1065 case ISD::TRUNCATE:
1066 case ISD::SIGN_EXTEND:
1067 case ISD::ZERO_EXTEND:
1068 case ISD::ANY_EXTEND:
1122 SDValue LoOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src0, Zero);
1123 SDValue LoOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoOpVT, Src1, Zero);
1125 SDValue HiOp0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src0, LoElts);
1126 SDValue HiOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiOpVT, Src1, LoElts);
1129 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LoMaskVT, Mask, Zero);
1131 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HiMaskVT, Mask, LoElts);
1134 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1136 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1138 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1155 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1170 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), N->getValueType(0),
1188 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1190 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1225 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1257 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1269 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1286 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1292 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0),
1309 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1310 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1311 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1327 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1328 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1330 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1358 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1359 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1360 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1361 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1362 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1363 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1364 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1365 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1366 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1367 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1368 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1369 case ISD::VSELECT:
1370 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1371 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1372 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1373 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1374 case ISD::VECTOR_SHUFFLE:
1377 case ISD::ADD:
1378 case ISD::AND:
1379 case ISD::BSWAP:
1380 case ISD::FADD:
1381 case ISD::FCOPYSIGN:
1382 case ISD::FDIV:
1383 case ISD::FMUL:
1384 case ISD::FPOW:
1385 case ISD::FREM:
1386 case ISD::FSUB:
1387 case ISD::MUL:
1388 case ISD::MULHS:
1389 case ISD::MULHU:
1390 case ISD::OR:
1391 case ISD::SDIV:
1392 case ISD::SREM:
1393 case ISD::UDIV:
1394 case ISD::UREM:
1395 case ISD::SUB:
1396 case ISD::XOR:
1400 case ISD::FPOWI:
1404 case ISD::SHL:
1405 case ISD::SRA:
1406 case ISD::SRL:
1410 case ISD::ANY_EXTEND:
1411 case ISD::FP_EXTEND:
1412 case ISD::FP_ROUND:
1413 case ISD::FP_TO_SINT:
1414 case ISD::FP_TO_UINT:
1415 case ISD::SIGN_EXTEND:
1416 case ISD::SINT_TO_FP:
1417 case ISD::TRUNCATE:
1418 case ISD::UINT_TO_FP:
1419 case ISD::ZERO_EXTEND:
1423 case ISD::CTLZ:
1424 case ISD::CTPOP:
1425 case ISD::CTTZ:
1426 case ISD::FABS:
1427 case ISD::FCEIL:
1428 case ISD::FCOS:
1429 case ISD::FEXP:
1430 case ISD::FEXP2:
1431 case ISD::FFLOOR:
1432 case ISD::FLOG:
1433 case ISD::FLOG10:
1434 case ISD::FLOG2:
1435 case ISD::FNEARBYINT:
1436 case ISD::FNEG:
1437 case ISD::FRINT:
1438 case ISD::FSIN:
1439 case ISD::FSQRT:
1440 case ISD::FTRUNC:
1443 case ISD::FMA:
1504 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
1506 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
1519 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1521 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
1559 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
1576 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1597 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0], NumOps);
1639 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT,
1647 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT,
1662 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
1674 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts);
1748 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1763 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
1798 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl,
1801 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
1803 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
1825 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &NewOps[0], NewOps.size());
1848 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &Ops[0], NumConcat);
1856 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
1888 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
1894 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1912 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1939 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, &Ops[0],NumConcat);
1946 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
1962 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
1972 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
1996 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2005 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2011 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], WidenNumElts);
2016 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(),
2023 ISD::LoadExtType ExtType = LD->getExtensionType();
2027 if (ExtType != ISD::NON_EXTLOAD)
2039 NewChain = DAG.getNode(ISD::TokenFactor, LD->getDebugLoc(), MVT::Other,
2051 return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
2082 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
2096 return DAG.getNode(ISD::SETCC, N->getDebugLoc(), WidenVT,
2151 return DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2178 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2179 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2180 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2181 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2182 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2183 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2185 case ISD::FP_EXTEND:
2186 case ISD::FP_TO_SINT:
2187 case ISD::FP_TO_UINT:
2188 case ISD::SINT_TO_FP:
2189 case ISD::UINT_TO_FP:
2190 case ISD::TRUNCATE:
2191 case ISD::SIGN_EXTEND:
2192 case ISD::ZERO_EXTEND:
2193 case ISD::ANY_EXTEND:
2232 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2235 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2252 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2253 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2281 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2284 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
2289 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(),
2295 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(),
2313 return DAG.getNode(ISD::TokenFactor, ST->getDebugLoc(),
2329 SDValue WideSETCC = DAG.getNode(ISD::SETCC, N->getDebugLoc(),
2336 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
2417 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
2424 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
2429 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
2432 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
2472 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
2473 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
2485 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &ConcatOps[0],
2499 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2519 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0),
2562 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
2571 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2585 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, &WidenOps[0],NumOps);
2591 ISD::LoadExtType ExtType) {
2620 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2633 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, &Ops[0], Ops.size());
2668 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
2677 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2684 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
2688 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
2696 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
2733 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2740 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
2742 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
2775 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, &Ops[0], NumConcat);
2779 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
2788 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2794 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &Ops[0], WidenNumElts);
