Lines Matching refs:ISD
93 // ISD Namespace
98 bool ISD::isBuildVectorAllOnes(const SDNode *N) {
100 if (N->getOpcode() == ISD::BITCAST)
103 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
108 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
138 N->getOperand(i).getOpcode() != ISD::UNDEF)
146 bool ISD::isBuildVectorAllZeros(const SDNode *N) {
148 if (N->getOpcode() == ISD::BITCAST)
151 if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
156 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF)
178 N->getOperand(i).getOpcode() != ISD::UNDEF)
184 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
186 bool ISD::isScalarToVector(const SDNode *N) {
187 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR)
190 if (N->getOpcode() != ISD::BUILD_VECTOR)
192 if (N->getOperand(0).getOpcode() == ISD::UNDEF)
199 if (V.getOpcode() != ISD::UNDEF)
206 /// and all operands of the specified node are ISD::UNDEF.
207 bool ISD::allOperandsUndef(const SDNode *N) {
215 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
223 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
228 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits
235 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
242 if (Operation > ISD::SETTRUE2)
245 return ISD::CondCode(Operation);
252 static int isSignedOp(ISD::CondCode Opcode) {
255 case ISD::SETEQ:
256 case ISD::SETNE: return 0;
257 case ISD::SETLT:
258 case ISD::SETLE:
259 case ISD::SETGT:
260 case ISD::SETGE: return 1;
261 case ISD::SETULT:
262 case ISD::SETULE:
263 case ISD::SETUGT:
264 case ISD::SETUGE: return 2;
272 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2,
276 return ISD::SETCC_INVALID;
282 if (Op > ISD::SETTRUE2)
286 if (isInteger && Op == ISD::SETUNE) // e.g. SETUGT | SETULT
287 Op = ISD::SETNE;
289 return ISD::CondCode(Op);
296 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2,
300 return ISD::SETCC_INVALID;
303 ISD::CondCode Result = ISD::CondCode(Op1 & Op2);
309 case ISD::SETUO : Result = ISD::SETFALSE; break; // SETUGT & SETULT
310 case ISD::SETOEQ: // SETEQ & SETU[LG]E
311 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE
312 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE
313 case ISD::SETOGT: Result = ISD::SETUGT ; break; // SETUGT & SETNE
368 case ISD::TargetExternalSymbol:
369 case ISD::ExternalSymbol:
372 case ISD::TargetConstant:
373 case ISD::Constant:
376 case ISD::TargetConstantFP:
377 case ISD::ConstantFP: {
381 case ISD::TargetGlobalAddress:
382 case ISD::GlobalAddress:
383 case ISD::TargetGlobalTLSAddress:
384 case ISD::GlobalTLSAddress: {
392 case ISD::BasicBlock:
395 case ISD::Register:
398 case ISD::RegisterMask:
401 case ISD::SRCVALUE:
404 case ISD::FrameIndex:
405 case ISD::TargetFrameIndex:
408 case ISD::JumpTable:
409 case ISD::TargetJumpTable:
413 case ISD::ConstantPool:
414 case ISD::TargetConstantPool: {
425 case ISD::TargetIndex: {
432 case ISD::LOAD: {
439 case ISD::STORE: {
446 case ISD::ATOMIC_CMP_SWAP:
447 case ISD::ATOMIC_SWAP:
448 case ISD::ATOMIC_LOAD_ADD:
449 case ISD::ATOMIC_LOAD_SUB:
450 case ISD::ATOMIC_LOAD_AND:
451 case ISD::ATOMIC_LOAD_OR:
452 case ISD::ATOMIC_LOAD_XOR:
453 case ISD::ATOMIC_LOAD_NAND:
454 case ISD::ATOMIC_LOAD_MIN:
455 case ISD::ATOMIC_LOAD_MAX:
456 case ISD::ATOMIC_LOAD_UMIN:
457 case ISD::ATOMIC_LOAD_UMAX:
458 case ISD::ATOMIC_LOAD:
459 case ISD
466 case ISD::PREFETCH: {
471 case ISD::VECTOR_SHUFFLE: {
478 case ISD::TargetBlockAddress:
479 case ISD::BlockAddress: {
511 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile,
535 case ISD::HANDLENODE:
536 case ISD::EH_LABEL:
635 N->NodeType = ISD::DELETED_NODE;
655 case ISD::HANDLENODE: return false; // noop.
656 case ISD::CONDCODE:
662 case ISD::ExternalSymbol:
665 case ISD::TargetExternalSymbol: {
672 case ISD::VALUETYPE: {
684 assert(N->getOpcode() != ISD::DELETED_NODE && "DELETED_NODE in CSEMap!");
685 assert(N->getOpcode() != ISD::EntryToken && "EntryToken in CSEMap!");
792 case ISD::BUILD_PAIR: {
806 case ISD::BUILD_VECTOR: {
877 TTI(0), OptLevel(OL), EntryNode(ISD::EntryToken, DebugLoc(),
927 getNode(ISD::ANY_EXTEND, DL, VT, Op) :
928 getNode(ISD::TRUNCATE, DL, VT, Op);
933 getNode(ISD::SIGN_EXTEND, DL, VT, Op) :
934 getNode(ISD::TRUNCATE, DL, VT, Op);
939 getNode(ISD::ZERO_EXTEND, DL, VT, Op) :
940 getNode(ISD::TRUNCATE, DL, VT, Op);
951 return getNode(ISD::AND, DL, Op.getValueType(), Op,
961 return getNode(ISD::XOR, DL, VT, Val, NegOne);
995 unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
1015 Result = getNode(ISD::BUILD_VECTOR, DebugLoc(), VT, &Ops[0], Ops.size());
1037 unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP;
1058 Result = getNode(ISD::BUILD_VECTOR, DebugLoc(), VT, &Ops[0], Ops.size());
1101 Opc = isTargetGA ? ISD::TargetGlobalTLSAddress : ISD::GlobalTLSAddress;
1103 Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress;
1123 unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex;
1141 unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable;
1165 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1192 unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
1213 AddNodeIDNode(ID, ISD::TargetIndex, getVTList(VT), 0, 0);
1230 AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
1275 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) {
1311 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF)
1331 if (N1.getOpcode() == ISD::UNDEF)
1337 bool N2Undef = N2.getOpcode() == ISD::UNDEF;
1371 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops, 2);
1395 ISD::CvtCode Code) {
1399 (Code == ISD::CVT_UU || Code == ISD::CVT_SS || Code == ISD::CVT_FF))
1404 AddNodeIDNode(ID, ISD::CONVERT_RNDSAT, getVTList(VT), &Ops[0], 5);
1418 AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0);
1432 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), 0, 0);
1447 AddNodeIDNode(ID, ISD::EH_LABEL, getVTList(MVT::Other), &Ops[0], 1);
1464 unsigned Opc = isTarget ? ISD::TargetBlockAddress : ISD::BlockAddress;
1487 AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
1503 AddNodeIDNode(ID, ISD::MDNODE_SDNODE, getVTList(MVT::Other), 0, 0);
1524 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1558 SDValue N2, ISD::CondCode Cond, DebugLoc dl) {
1562 case ISD::SETFALSE:
1563 case ISD::SETFALSE2: return getConstant(0, VT);
1564 case ISD::SETTRUE:
1565 case ISD::SETTRUE2: return getConstant(1, VT);
1567 case ISD::SETOEQ:
1568 case ISD::SETOGT:
1569 case ISD::SETOGE:
1570 case ISD::SETOLT:
1571 case ISD::SETOLE:
1572 case ISD::SETONE:
1573 case ISD::SETO:
1574 case ISD::SETUO:
1575 case ISD::SETUEQ:
1576 case ISD::SETUNE:
1588 case ISD::SETEQ: return getConstant(C1 == C2, VT);
1589 case ISD::SETNE: return getConstant(C1 != C2, VT);
1590 case ISD::SETULT: return getConstant(C1.ult(C2), VT);
1591 case ISD::SETUGT: return getConstant(C1.ugt(C2), VT);
1592 case ISD::SETULE: return getConstant(C1.ule(C2), VT);
1593 case ISD::SETUGE: return getConstant(C1.uge(C2), VT);
1594 case ISD::SETLT: return getConstant(C1.slt(C2), VT);
1595 case ISD::SETGT: return getConstant(C1.sgt(C2), VT);
1596 case ISD::SETLE: return getConstant(C1.sle(C2), VT);
1597 case ISD::SETGE: return getConstant(C1.sge(C2), VT);
1606 case ISD::SETEQ: if (R==APFloat::cmpUnordered)
1609 case ISD::SETOEQ: return getConstant(R==APFloat::cmpEqual, VT);
1610 case ISD::SETNE: if (R==APFloat::cmpUnordered)
1613 case ISD::SETONE: return getConstant(R==APFloat::cmpGreaterThan ||
1615 case ISD::SETLT: if (R==APFloat::cmpUnordered)
1618 case ISD::SETOLT: return getConstant(R==APFloat::cmpLessThan, VT);
1619 case ISD::SETGT: if (R==APFloat::cmpUnordered)
1622 case ISD::SETOGT: return getConstant(R==APFloat::cmpGreaterThan, VT);
1623 case ISD::SETLE: if (R==APFloat::cmpUnordered)
1626 case ISD::SETOLE: return getConstant(R==APFloat::cmpLessThan ||
1628 case ISD::SETGE: if (R==APFloat::cmpUnordered)
1631 case ISD::SETOGE: return getConstant(R==APFloat::cmpGreaterThan ||
1633 case ISD::SETO: return getConstant(R!=APFloat::cmpUnordered, VT);
1634 case ISD::SETUO: return getConstant(R==APFloat::cmpUnordered, VT);
1635 case ISD::SETUEQ: return getConstant(R==APFloat::cmpUnordered ||
1637 case ISD::SETUNE: return getConstant(R!=APFloat::cmpEqual, VT);
1638 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered ||
1640 case ISD::SETUGT: return getConstant(R==APFloat::cmpGreaterThan ||
1642 case ISD::SETULE: return getConstant(R!=APFloat::cmpGreaterThan, VT);
1643 case ISD::SETUGE: return getConstant(R!=APFloat::cmpLessThan, VT);
1647 return getSetCC(dl, VT, N2, N1, ISD::getSetCCSwappedOperands(Cond));
1692 case ISD::Constant:
1697 case ISD::AND:
1709 case ISD::OR:
1720 case ISD::XOR: {
1733 case ISD::MUL: {
1756 case ISD::UDIV: {
1774 case ISD::SELECT:
1784 case ISD::SELECT_CC:
1794 case ISD::SADDO:
1795 case ISD::UADDO:
1796 case ISD::SSUBO:
1797 case ISD::USUBO:
1798 case ISD::SMULO:
1799 case ISD::UMULO:
1803 case ISD::SETCC:
1809 case ISD::SHL:
1826 case ISD::SRL:
1844 case ISD::SRA:
1872 case ISD::SIGN_EXTEND_INREG: {
1908 case ISD::CTTZ:
1909 case ISD::CTTZ_ZERO_UNDEF:
1910 case ISD::CTLZ:
1911 case ISD::CTLZ_ZERO_UNDEF:
1912 case ISD::CTPOP: {
1918 case ISD::LOAD: {
1920 if (ISD::isZEXTLoad(Op.getNode())) {
1929 case ISD::ZERO_EXTEND: {
1941 case ISD::SIGN_EXTEND: {
1967 case ISD::ANY_EXTEND: {
1977 case ISD::TRUNCATE: {
1988 case ISD::AssertZext: {
1996 case ISD::FGETSIGN:
2001 case ISD::SUB: {
2024 case ISD::ADD:
2025 case ISD::ADDE: {
2038 if (Op.getOpcode() == ISD::ADD) {
2051 case ISD::SREM:
2076 case ISD::UREM: {
2099 case ISD::FrameIndex:
2100 case ISD::TargetFrameIndex:
2109 if (Op.getOpcode() < ISD::BUILTIN_OP_END)
2112 case ISD::INTRINSIC_WO_CHAIN:
2113 case ISD::INTRINSIC_W_CHAIN:
2114 case ISD::INTRINSIC_VOID:
2138 case ISD::AssertSext:
2141 case ISD::AssertZext:
2145 case ISD::Constant: {
2150 case ISD::SIGN_EXTEND:
2154 case ISD::SIGN_EXTEND_INREG:
2163 case ISD::SRA:
2171 case ISD::SHL:
2180 case ISD::AND:
2181 case ISD::OR:
2182 case ISD::XOR: // NOT is handled here.
2194 case ISD::SELECT:
2200 case ISD::SADDO:
2201 case ISD::UADDO:
2202 case ISD::SSUBO:
2203 case ISD::USUBO:
2204 case ISD::SMULO:
2205 case ISD::UMULO:
2209 case ISD::SETCC:
2215 case ISD::ROTL:
2216 case ISD::ROTR:
2221 if (Op.getOpcode() == ISD::ROTR)
2230 case ISD::ADD:
2257 case ISD::SUB:
2284 case ISD::TRUNCATE:
2295 case ISD::SEXTLOAD: // '17' bits known
2298 case ISD::ZEXTLOAD: // '16' bits known
2305 if (Op.getOpcode() >= ISD::BUILTIN_OP_END ||
2306 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
2307 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
2308 Op.getOpcode() == ISD::INTRINSIC_VOID) {
2338 /// ISD::ADD with a ConstantSDNode on the right-hand side, or if it is an
2339 /// ISD::OR with a ConstantSDNode that is guaranteed to have the same
2343 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
2347 if (Op.getOpcode() == ISD::OR &&
2378 case ISD::OR:
2426 case ISD::SIGN_EXTEND:
2428 case ISD::ANY_EXTEND:
2429 case ISD::ZERO_EXTEND:
2430 case ISD::TRUNCATE:
2432 case ISD::UINT_TO_FP:
2433 case ISD::SINT_TO_FP: {
2437 Opcode==ISD::SINT_TO_FP,
2441 case ISD::BITCAST:
2447 case ISD::BSWAP:
2449 case ISD::CTPOP:
2451 case ISD::CTLZ:
2452 case ISD::CTLZ_ZERO_UNDEF:
2454 case ISD::CTTZ:
2455 case ISD::CTTZ_ZERO_UNDEF:
2464 case ISD::FNEG:
2467 case ISD::FABS:
2470 case ISD::FCEIL: {
2476 case ISD::FTRUNC: {
2482 case ISD::FFLOOR: {
2488 case ISD::FP_EXTEND: {
2496 case ISD::FP_TO_SINT:
2497 case ISD::FP_TO_UINT: {
2503 Opcode==ISD::FP_TO_SINT,
2510 case ISD::BITCAST:
2521 case ISD::TokenFactor:
2522 case ISD::MERGE_VALUES:
2523 case ISD::CONCAT_VECTORS:
2525 case ISD::FP_ROUND: llvm_unreachable("Invalid method to make FP_ROUND node");
2526 case ISD::FP_EXTEND:
2534 if (Operand.getOpcode() == ISD::UNDEF)
2537 case ISD::SIGN_EXTEND:
2547 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
2549 else if (OpOpcode == ISD::UNDEF)
2553 case ISD::ZERO_EXTEND:
2563 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
2564 return getNode(ISD::ZERO_EXTEND, DL, VT,
2566 else if (OpOpcode == ISD::UNDEF)
2570 case ISD::ANY_EXTEND:
2581 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
2582 OpOpcode == ISD::ANY_EXTEND)
2585 else if (OpOpcode == ISD::UNDEF)
2589 if (OpOpcode == ISD::TRUNCATE) {
2595 case ISD::TRUNCATE:
2605 if (OpOpcode == ISD::TRUNCATE)
2606 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2607 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
2608 OpOpcode == ISD::ANY_EXTEND) {
2614 return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
2617 if (OpOpcode == ISD::UNDEF)
2620 case ISD::BITCAST:
2625 if (OpOpcode == ISD::BITCAST) // bitconv(bitconv(x)) -> bitconv(x)
2626 return getNode(ISD::BITCAST, DL, VT, Operand.getOperand(0));
2627 if (OpOpcode == ISD::UNDEF)
2630 case ISD::SCALAR_TO_VECTOR:
2637 if (OpOpcode == ISD::UNDEF)
2640 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
2646 case ISD::FNEG:
2648 if (getTarget().Options.UnsafeFPMath && OpOpcode == ISD::FSUB)
2649 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
2651 if (OpOpcode == ISD::FNEG) // --X -> X
2654 case ISD::FABS:
2655 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
2656 return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0));
2725 case ISD::ADD:
2728 case ISD::SUB:
2731 case ISD::MUL:
2734 case ISD::UDIV:
2739 case ISD::UREM:
2744 case ISD::SDIV:
2749 case ISD::SREM:
2754 case ISD::AND:
2757 case ISD::OR:
2760 case ISD::XOR:
2763 case ISD::SHL:
2766 case ISD::SRL:
2769 case ISD::SRA:
2772 case ISD::ROTL:
2775 case ISD::ROTR:
2788 return getNode(ISD::BUILD_VECTOR, DebugLoc(), VT, Outputs.data(),
2798 case ISD::TokenFactor:
2802 if (N1.getOpcode() == ISD::EntryToken) return N2;
2803 if (N2.getOpcode() == ISD::EntryToken) return N1;
2806 case ISD::CONCAT_VECTORS:
2808 if (N1.getOpcode() == ISD::UNDEF &&
2809 N2.getOpcode() == ISD::UNDEF)
2814 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
2815 N2.getOpcode() == ISD::BUILD_VECTOR) {
2819 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
2822 case ISD::AND:
2833 case ISD::OR:
2834 case ISD::XOR:
2835 case ISD::ADD:
2836 case ISD::SUB:
2845 case ISD::UDIV:
2846 case ISD::UREM:
2847 case ISD::MULHU:
2848 case ISD::MULHS:
2849 case ISD::MUL:
2850 case ISD::SDIV:
2851 case ISD::SREM:
2856 case ISD::FADD:
2857 case ISD::FSUB:
2858 case ISD::FMUL:
2859 case ISD::FDIV:
2860 case ISD::FREM:
2862 if (Opcode == ISD::FADD) {
2871 } else if (Opcode == ISD::FSUB) {
2876 } else if (Opcode == ISD::FMUL) {
2900 case ISD::FCOPYSIGN: // N1 and result must match. N1/N2 need not match.
2906 case ISD::SHL:
2907 case ISD::SRA:
2908 case ISD::SRL:
2909 case ISD::ROTL:
2910 case ISD::ROTR:
2933 case ISD::FP_ROUND_INREG: {
2949 case ISD::FP_ROUND:
2956 case ISD::AssertSext:
2957 case ISD::AssertZext: {
2969 case ISD::SIGN_EXTEND_INREG: {
2992 case ISD::EXTRACT_VECTOR_ELT:
2994 if (N1.getOpcode() == ISD::UNDEF)
3000 N1.getOpcode() == ISD::CONCAT_VECTORS &&
3004 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
3012 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
3026 if (N1.getOpcode() == ISD::INSERT_VECTOR_ELT) {
3041 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2);
3045 case ISD::EXTRACT_ELEMENT:
3055 if (N1.getOpcode() == ISD::BUILD_PAIR)
3066 case ISD::EXTRACT_SUBVECTOR: {
3113 case ISD::FADD:
3118 case ISD::FSUB:
3123 case ISD::FMUL:
3128 case ISD::FDIV:
3133 case ISD::FREM :
3138 case ISD::FCOPYSIGN:
3145 if (Opcode == ISD::FP_ROUND) {
3157 if (N1.getOpcode() == ISD::UNDEF) {
3162 case ISD::FP_ROUND_INREG:
3163 case ISD::SIGN_EXTEND_INREG:
3164 case ISD::SUB:
3165 case ISD::FSUB:
3166 case ISD::FDIV:
3167 case ISD::FREM:
3168 case ISD::SRA:
3170 case ISD::UDIV:
3171 case ISD::SDIV:
3172 case ISD::UREM:
3173 case ISD::SREM:
3174 case ISD::SRL:
3175 case ISD::SHL:
3186 if (N2.getOpcode() == ISD::UNDEF) {
3188 case ISD::XOR:
3189 if (N1.getOpcode() == ISD::UNDEF)
3194 case ISD::ADD:
3195 case ISD::ADDC:
3196 case ISD::ADDE:
3197 case ISD::SUB:
3198 case ISD::UDIV:
3199 case ISD::SDIV:
3200 case ISD::UREM:
3201 case ISD::SREM:
3203 case ISD::FADD:
3204 case ISD::FSUB:
3205 case ISD::FMUL:
3206 case ISD::FDIV:
3207 case ISD::FREM:
3211 case ISD::MUL:
3212 case ISD::AND:
3213 case ISD::SRL:
3214 case ISD::SHL:
3220 case ISD::OR:
3226 case ISD::SRA:
3260 case ISD::CONCAT_VECTORS:
3263 if (N1.getOpcode() == ISD::BUILD_VECTOR &&
3264 N2.getOpcode() == ISD::BUILD_VECTOR &&
3265 N3.getOpcode() == ISD::BUILD_VECTOR) {
3270 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
3273 case ISD::SETCC: {
3279 case ISD::SELECT:
3288 case ISD::VECTOR_SHUFFLE:
3290 case ISD::INSERT_SUBVECTOR: {
3314 case ISD::BITCAST:
3378 return getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other,
3386 assert(Value.getOpcode() != ISD::UNDEF);
3397 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Value);
3402 Value = DAG.getNode(ISD::MUL, dl, VT, Value, DAG.getConstant(Magic, VT));
3422 return DAG.getNode(ISD::BITCAST, dl, VT,
3456 return DAG.getNode(ISD::ADD, Base.getDebugLoc(),
3465 if (Src.getOpcode() == ISD::GlobalAddress)
3467 else if (Src.getOpcode() == ISD::ADD &&
3468 Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
3469 Src.getOperand(1).getOpcode() == ISD::Constant) {
3538 if (TLI.isOperationLegalOrCustom(ISD::STORE, NewVT) &&
3542 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::f64) &&
3592 if (Src.getOpcode() == ISD::UNDEF)
3683 Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
3698 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3710 if (Src.getOpcode() == ISD::UNDEF)
3764 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3779 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3789 if (Src.getOpcode() == ISD::UNDEF)
3849 Value = DAG.getNode(ISD::TRUNCATE, dl, VT, MemSetValue);
3863 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4029 Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
4031 Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
4071 if (Opcode != ISD::ATOMIC_STORE)
4073 if (Opcode != ISD::ATOMIC_LOAD)
4089 assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
4131 if (Opcode != ISD::ATOMIC_STORE)
4133 if (Opcode != ISD::ATOMIC_LOAD)
4150 assert((Opcode == ISD::ATOMIC_LOAD_ADD ||
4151 Opcode == ISD::ATOMIC_LOAD_SUB ||
4152 Opcode == ISD::ATOMIC_LOAD_AND ||
4153 Opcode == ISD::ATOMIC_LOAD_OR ||
4154 Opcode == ISD::ATOMIC_LOAD_XOR ||
4155 Opcode == ISD::ATOMIC_LOAD_NAND ||
4156 Opcode == ISD::ATOMIC_LOAD_MIN ||
4157 Opcode == ISD::ATOMIC_LOAD_MAX ||
4158 Opcode == ISD::ATOMIC_LOAD_UMIN ||
4159 Opcode == ISD::ATOMIC_LOAD_UMAX ||
4160 Opcode == ISD::ATOMIC_SWAP ||
4161 Opcode == ISD::ATOMIC_STORE) &&
4166 SDVTList VTs = Opcode == ISD::ATOMIC_STORE ? getVTList(MVT::Other) :
4204 if (Opcode != ISD::ATOMIC_STORE)
4206 if (Opcode != ISD::ATOMIC_LOAD)
4223 assert(Opcode == ISD::ATOMIC_LOAD && "Invalid Atomic Op");
4253 return getNode(ISD::MERGE_VALUES, dl, getVTList(&VTs[0], NumOps),
4296 assert((Opcode == ISD::INTRINSIC_VOID ||
4297 Opcode == ISD::INTRINSIC_W_CHAIN ||
4298 Opcode == ISD::PREFETCH ||
4299 Opcode == ISD::LIFETIME_START ||
4300 Opcode == ISD::LIFETIME_END ||
4302 (int)Opcode >= ISD::FIRST_TARGET_MEMORY_OPCODE)) &&
4338 if (Ptr.getOpcode() != ISD::ADD ||
4356 if (OffsetOp.getOpcode() == ISD::UNDEF)
4363 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
4396 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
4401 ExtType = ISD::NON_EXTLOAD;
4402 } else if (ExtType == ISD::NON_EXTLOAD) {
4417 bool Indexed = AM != ISD::UNINDEXED;
4418 assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
4425 AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
4451 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
4456 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
4462 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
4470 SDValue Offset, ISD::MemIndexedMode AM) {
4472 assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
4516 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4518 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile(),
4526 SDNode *N = new (NodeAllocator) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED,
4584 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4586 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile(),
4594 SDNode *N = new (NodeAllocator) StoreSDNode(Ops, dl, VTs, ISD::UNINDEXED,
4603 SDValue Offset, ISD::MemIndexedMode AM) {
4605 assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
4610 AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
4632 return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 4);
4663 case ISD::SELECT_CC: {
4673 case ISD::BR_CC: {
4731 case ISD::SRA_PARTS:
4732 case ISD::SRL_PARTS:
4733 case ISD::SHL_PARTS:
4734 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4737 else if (N3.getOpcode() == ISD::AND)
5828 assert(AllNodes.front().getOpcode() == ISD::EntryToken &&
5903 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(),
5916 SubclassData = encodeMemSDNodeFlags(0, ISD::UNINDEXED, MMO->isVolatile(),
6036 if (getOpcode() == ISD::TokenFactor) {
6119 Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl,
6134 case ISD::VSELECT:
6135 Scalars.push_back(getNode(ISD::SELECT, dl, EltVT,
6138 case ISD::SHL:
6139 case ISD::SRA:
6140 case ISD::SRL:
6141 case ISD::ROTL:
6142 case ISD::ROTR:
6147 case ISD::SIGN_EXTEND_INREG:
6148 case ISD::FP_ROUND_INREG: {
6160 return getNode(ISD::BUILD_VECTOR, dl,
6179 if (Loc.getOpcode() == ISD::FrameIndex) {
6180 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6276 // of the vector is an ISD::UNDEF value) are set in SplatUndef and cleared
6288 if (OpVal.getOpcode() == ISD::UNDEF)
