Lines Matching refs:ISD
104 ISD::CondCode &CCCode,
112 case ISD::SETEQ:
113 case ISD::SETOEQ:
117 case ISD::SETNE:
118 case ISD::SETUNE:
122 case ISD::SETGE:
123 case ISD::SETOGE:
127 case ISD::SETLT:
128 case ISD::SETOLT:
132 case ISD::SETLE:
133 case ISD::SETOLE:
137 case ISD::SETGT:
138 case ISD::SETOGT:
142 case ISD::SETUO:
146 case ISD::SETO:
154 case ISD::SETONE:
159 case ISD::SETUGT:
163 case ISD::SETUGE:
167 case ISD::SETULT:
171 case ISD::SETULE:
175 case ISD::SETUEQ:
190 SDValue Tmp = DAG.getNode(ISD::SETCC, dl, getSetCCResultType(RetVT),
193 NewLHS = DAG.getNode(ISD::SETCC, dl, getSetCCResultType(RetVT), NewLHS,
195 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
267 // FIXME: ISD::SELECT, ISD::SELECT_CC
270 case ISD::XOR:
271 case ISD::AND:
272 case ISD::OR: {
276 if (Op.getOpcode() == ISD::XOR &&
329 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
331 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
334 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
377 if (Op.getOpcode() != ISD::UNDEF)
386 case ISD::Constant:
391 case ISD::AND:
439 case ISD::OR:
473 case ISD::XOR:
497 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
515 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
543 case ISD::SELECT:
561 case ISD::SELECT_CC:
579 case ISD::SHL:
591 if (InOp.getOpcode() == ISD::SRL &&
595 unsigned Opc = ISD::SHL;
599 Opc = ISD::SRL;
616 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
621 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
626 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
630 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
641 case ISD::SRL:
655 if (InOp.getOpcode() == ISD::SHL &&
659 unsigned Opc = ISD::SRL;
663 Opc = ISD::SHL;
685 case ISD::SRA:
692 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
724 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
732 case ISD::SIGN_EXTEND_INREG: {
748 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
795 case ISD::ZERO_EXTEND: {
804 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
817 case ISD::SIGN_EXTEND: {
826 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
844 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
858 case ISD::ANY_EXTEND: {
870 case ISD::TRUNCATE: {
888 case ISD::SRL:
892 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
913 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
916 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
928 case ISD::AssertZext: {
942 case ISD::BITCAST:
950 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
951 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
956 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
959 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
962 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
968 case ISD::ADD:
969 case ISD::MUL:
970 case ISD::SUB: {
1008 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1009 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1010 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1011 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1022 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1023 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1024 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1025 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1038 if (Val.getOpcode() == ISD::SHL)
1046 if (Val.getOpcode() == ISD::SRL)
1068 ISD::CondCode Cond, bool foldBooleans,
1075 case ISD::SETFALSE:
1076 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1077 case ISD::SETTRUE:
1078 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1084 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1092 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1093 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1094 N0.getOperand(1).getOpcode() == ISD::Constant) {
1097 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1099 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1102 Cond = ISD::SETNE;
1106 Cond = ISD::SETEQ;
1116 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1119 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1127 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1128 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1130 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1131 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1140 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1143 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1147 } else if (N0->getOpcode() == ISD::AND) {
1156 if (LN0->getExtensionType() == ISD
1165 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1167 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
1178 N0.getOpcode() == ISD::AND && C1 == 0 &&
1191 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1217 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1224 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1233 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1241 case ISD::SETUGT:
1242 case ISD::SETUGE:
1243 case ISD::SETEQ: return DAG.getConstant(0, VT);
1244 case ISD::SETULT:
1245 case ISD::SETULE:
1246 case ISD::SETNE: return DAG.getConstant(1, VT);
1247 case ISD::SETGT:
1248 case ISD::SETGE:
1251 case ISD::SETLT:
1252 case ISD::SETLE:
1262 case ISD::SETEQ:
1263 case ISD::SETNE:
1264 case ISD::SETUGT:
1265 case ISD::SETUGE:
1266 case ISD::SETULT:
1267 case ISD::SETULE: {
1270 (isOperationLegal(ISD::SETCC, newVT) &&
1280 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1281 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1290 return DAG.getConstant(Cond == ISD::SETNE, VT);
1298 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1311 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1313 if (N0.getOpcode() == ISD::SETCC &&
1315 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1317 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1319 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1320 CC = ISD::getSetCCInverse(CC,
1325 if ((N0.getOpcode() == ISD::XOR ||
1326 (N0.getOpcode() == ISD::AND &&
1327 N0.getOperand(0).getOpcode() == ISD::XOR &&
1339 if (N0.getOpcode() == ISD::XOR)
1342 assert(N0.getOpcode() == ISD::AND &&
1343 N0.getOperand(0).getOpcode() == ISD::XOR);
1345 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1351 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1357 if (Op0.getOpcode() == ISD::TRUNCATE)
1360 if ((Op0.getOpcode() == ISD::XOR) &&
1361 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1362 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1364 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1368 if (Op0.getOpcode() == ISD::AND &&
1373 Op0 = DAG.getNode(ISD::AND, dl, VT,
1374 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1377 Op0 = DAG.getNode(ISD::AND, dl, VT,
1378 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1383 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1385 if (Op0.getOpcode() == ISD::AssertZext &&
1389 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1395 if (ISD::isSignedIntSetCC(Cond)) {
1404 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1409 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1412 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1417 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1420 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1422 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1424 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1426 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1430 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1431 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1433 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1434 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1437 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1440 ISD::SETEQ);
1442 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1445 ISD::SETEQ);
1451 if (Cond == ISD::SETUGT &&
1455 ISD::SETLT);
1458 if (Cond == ISD::SETULT &&
1463 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1467 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1470 N0.getOpcode() == ISD::AND)
1475 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1478 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1479 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1482 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1486 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1487 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1496 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1497 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1506 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1512 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1513 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1514 bool AdjOne = (Cond == ISDISD::SETUGT);
1521 ISD::CondCode NewCond = Cond;
1525 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1534 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1552 switch (ISD::getUnorderedFlavor(Cond)) {
1567 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1578 if (Cond == ISD::SETOEQ &&
1579 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1580 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1581 if (Cond == ISD::SETUEQ &&
1582 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1583 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1584 if (Cond == ISD::SETUNE &&
1585 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1586 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1587 if (Cond == ISD::SETONE &&
1588 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1589 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1591 if (Cond == ISD::SETOEQ &&
1592 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1593 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1594 if (Cond == ISD::SETUEQ &&
1595 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1596 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1597 if (Cond == ISD::SETUNE &&
1598 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1599 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1600 if (Cond == ISD::SETONE &&
1601 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1602 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1615 EqVal = ISD::isTrueWhenEqual(Cond);
1618 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1626 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1629 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1633 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1639 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1641 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1642 N0.getOpcode() == ISD::XOR) {
1667 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1675 if (N0.getOpcode() == ISD::XOR)
1689 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1717 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1719 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1729 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1730 N1.getOpcode() == ISD::XOR) {
1740 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1742 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1755 if (N0.getOpcode() == ISD::AND)
1758 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1763 if (N1.getOpcode() == ISD::AND)
1766 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1778 case ISD::SETEQ: // X == Y -> ~(X^Y)
1779 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1784 case ISD::SETNE: // X != Y --> (X^Y)
1785 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
1787 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
1788 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
1790 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
1794 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
1795 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
1797 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
1801 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
1802 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
1804 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
1808 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
1809 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
1811 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
1818 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1838 if (N->getOpcode() == ISD::ADD) {
1936 if (Op.getOpcode() == ISD::BasicBlock) {
1951 if (Op.getOpcode() == ISD::ADD) {
2451 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
2461 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2464 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2485 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2486 isOperationLegalOrCustom(ISD::MULHS, VT))
2487 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2489 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2490 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2491 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2498 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2504 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2510 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2517 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2521 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2524 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2550 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2562 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2563 isOperationLegalOrCustom(ISD::MULHU, VT))
2564 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2565 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2566 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2567 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2577 return DAG.getNode(ISD::SRL, dl, VT, Q,
2580 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2583 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2587 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2590 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
