Lines Matching defs:NewMIs
1196 SmallVector<MachineInstr *, 2> NewMIs;
1199 NewMIs)) {
1203 assert(NewMIs.size() == 2 &&
1206 NewMIs[1]->addRegisterKilled(Reg, TRI);
1210 MBB->insert(mi, NewMIs[0]);
1211 MBB->insert(mi, NewMIs[1]);
1213 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1214 << "2addr: NEW INST: " << *NewMIs[1]);
1217 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1218 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1219 MachineBasicBlock::iterator NewMI = NewMIs[1];
1225 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1235 if (NewMIs[0]->killsRegister(MO.getReg()))
1236 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1238 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1240 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1244 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1245 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1247 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1249 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1254 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1270 MachineBasicBlock::iterator Begin(NewMIs[0]);
1271 MachineBasicBlock::iterator End(NewMIs[1]);
1275 mi = NewMIs[1];
1281 NewMIs[0]->eraseFromParent();
1282 NewMIs[1]->eraseFromParent();
