Cross Reference: /external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines Matching refs:RegState
982       MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
983       MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
985         MIB.addReg(DestReg, RegState::ImplicitDefine);
1014         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1015         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1016         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1018           MIB.addReg(DestReg, RegState::ImplicitDefine);
1034         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1035         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1036         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1037         MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1039           MIB.addReg(DestReg, RegState::ImplicitDefine);
1050       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1051       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1052       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1053       MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1054       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1055       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1056       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1057       MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1059         MIB.addReg(DestReg, RegState::ImplicitDefine);
1177   MIB.addReg(SrcRegS, RegState::Implicit);
1795       .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
3846       AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3868       AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
3869                         .addReg(DReg, RegState::Undef)
3874       MIB.addReg(SrcReg, RegState::Implicit);
3897       MIB.addReg(DReg, RegState::Define)
3905       MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
3907         MIB.addReg(ImplicitSReg, RegState::Implicit);
3933         MIB.addReg(DDst, RegState::Define)
3940         MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
3941         MIB.addReg(SrcReg, RegState::Implicit);
3943           MIB.addReg(ImplicitSReg, RegState::Implicit);
3978         NewMIB.addReg(SrcReg, RegState::Implicit);
3981       MIB.addReg(DDst, RegState::Define);
3997         MIB.addReg(SrcReg, RegState::Implicit);
4001       MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4003         MIB.addReg(ImplicitSReg, RegState::Implicit);
OpenGrok
