Cross Reference: /external/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

Lines Matching refs:addReg
391   MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393     MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395     MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397     MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
428   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
466   MIB.addReg(D0, getUndefRegState(SrcIsUndef));
468     MIB.addReg(D1, getUndefRegState(SrcIsUndef));
470     MIB.addReg(D2, getUndefRegState(SrcIsUndef));
472     MIB.addReg(D3, getUndefRegState(SrcIsUndef));
522     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
524       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
526       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
528       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
549   MIB.addReg(D0, SrcFlags);
551     MIB.addReg(D1, SrcFlags);
553     MIB.addReg(D2, SrcFlags);
555     MIB.addReg(D3, SrcFlags);
570     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
596   MIB.addReg(D0);
628       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
629       .addReg(DstReg);
639     LO16.addImm(Pred).addReg(PredReg).addReg(0);
640     HI16.addImm(Pred).addReg(PredReg).addReg(0);
658     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
659     .addReg(DstReg);
676   LO16.addImm(Pred).addReg(PredReg);
677   HI16.addImm(Pred).addReg(PredReg);
695         .addReg(MI.getOperand(2).getReg(),
698         .addReg(MI.getOperand(4).getReg());
708         .addReg(MI.getOperand(2).getReg(),
711         .addReg(MI.getOperand(4).getReg())
712         .addReg(0); // 's' bit
720         .addReg(MI.getOperand(2).getReg(),
724         .addReg(MI.getOperand(5).getReg())
725         .addReg(0); // 's' bit
734         .addReg(MI.getOperand(2).getReg(),
736         .addReg(MI.getOperand(3).getReg(),
740         .addReg(MI.getOperand(6).getReg())
741         .addReg(0); // 's' bit
751         .addReg(MI.getOperand(4).getReg());
763         .addReg(MI.getOperand(4).getReg())
764         .addReg(0); // 's' bit
774         .addReg(MI.getOperand(4).getReg())
775         .addReg(0); // 's' bit
815                                       .addReg(ARM::R6, RegState::Kill)
833         .addReg(ARM::CPSR, RegState::Define);
844         .addReg(0);
874         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
875         .addReg(DstReg)
911         .addReg(DstReg)
922         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
923         .addReg(DstReg).addImm(LabelId);
961       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
962         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
965       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
992       MIB.addReg(D0).addReg(D1);
1017       MIB.addReg(DReg);
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