Cross Reference: /external/llvm/lib/Target/ARM/ARMFastISel.cpp

Lines Matching refs:RegState
310                    .addReg(Op0, Op0IsKill * RegState::Kill));
313                    .addReg(Op0, Op0IsKill * RegState::Kill));
330                    .addReg(Op0, Op0IsKill * RegState::Kill)
331                    .addReg(Op1, Op1IsKill * RegState::Kill));
334                    .addReg(Op0, Op0IsKill * RegState::Kill)
335                    .addReg(Op1, Op1IsKill * RegState::Kill));
353                    .addReg(Op0, Op0IsKill * RegState::Kill)
354                    .addReg(Op1, Op1IsKill * RegState::Kill)
355                    .addReg(Op2, Op2IsKill * RegState::Kill));
358                    .addReg(Op0, Op0IsKill * RegState::Kill)
359                    .addReg(Op1, Op1IsKill * RegState::Kill)
360                    .addReg(Op2, Op2IsKill * RegState::Kill));
377                    .addReg(Op0, Op0IsKill * RegState::Kill)
381                    .addReg(Op0, Op0IsKill * RegState::Kill)
399                    .addReg(Op0, Op0IsKill * RegState
403                    .addReg(Op0, Op0IsKill * RegState::Kill)
422                    .addReg(Op0, Op0IsKill * RegState::Kill)
423                    .addReg(Op1, Op1IsKill * RegState::Kill)
427                    .addReg(Op0, Op0IsKill * RegState::Kill)
428                    .addReg(Op1, Op1IsKill * RegState::Kill)
2021                       .addReg(NextVA.getLocReg(), RegState::Define)
2173     MIB.addReg(RetRegs[i], RegState::Implicit);
2274     MIB.addReg(RegArgs[i], RegState::Implicit);
2418     MIB.addReg(RegArgs[i], RegState::Implicit);
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