Lines Matching refs:NewOpc
2448 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2450 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
5247 unsigned NewOpc = 0;
5252 NewOpc = ARMISD::VMULLs;
5257 NewOpc = ARMISD::VMULLu;
5262 NewOpc = ARMISD::VMULLs;
5265 NewOpc = ARMISD::VMULLu;
5269 NewOpc = ARMISD::VMULLu;
5274 if (!NewOpc) {
5293 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
5308 DAG.getNode(NewOpc, DL, VT,
5310 DAG.getNode(NewOpc, DL, VT,
7030 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7040 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7054 unsigned NewOpc;
7057 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7058 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7059 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7061 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7397 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7398 if (NewOpc) {
7401 MCID = &TII->get(NewOpc);
7416 assert(!NewOpc && "Optional cc_out operand required");
7435 assert(!NewOpc && "Optional cc_out operand required");
8633 unsigned NewOpc = 0;
8639 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
8641 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
8643 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
8645 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
8647 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
8649 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
8651 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
8653 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
8655 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
8657 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
8659 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
8661 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
8663 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
8665 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
8672 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
8673 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
8674 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
8717 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
8752 unsigned NewOpc = 0;
8756 NewOpc = ARMISD::VLD2DUP;
8759 NewOpc = ARMISD::VLD3DUP;
8762 NewOpc = ARMISD::VLD4DUP;
8791 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
