Home | History | Annotate | Download | only in ARM

Lines Matching full:reglist

693 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
707     PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
710   let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
720                          (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
733                 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
737 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
747 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1382 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1384                            (tPOP pred:$p, reglist:$regs)>;