Lines Matching refs:ISD
177 int ISD = TLI->InstructionOpcodeToISD(Opcode);
178 assert(ISD && "Invalid opcode");
183 { ISD::FP_ROUND, MVT::v2f64, 2 },
184 { ISD::FP_EXTEND, MVT::v2f32, 2 },
185 { ISD::FP_EXTEND, MVT::v4f32, 4 }
188 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
189 ISD == ISD::FP_EXTEND)) {
192 ISD, LT.second);
207 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
208 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
209 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
210 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
211 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
212 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
215 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 16*2 + 4*4 },
216 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 16*2 + 4*3 },
217 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 8*2 + 2*4 },
218 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 8*2 + 2*3 },
219 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4*1 + 16*2 + 2*1 },
220 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2*1 + 8*2 + 1 },
223 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
224 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
226 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
227 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
228 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
229 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
230 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
231 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
233 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
234 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
235 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
236 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
237 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
238 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
239 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
240 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
241 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
242 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
243 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
244 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
245 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
247 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
248 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
249 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
250 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
251 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
252 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
255 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
256 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
258 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
259 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
260 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
261 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
262 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
263 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
265 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
266 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
267 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
268 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
269 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
270 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
276 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
283 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
284 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
285 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
286 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
287 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
288 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
289 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
290 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
291 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
292 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
293 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
294 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
295 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
296 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
297 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
298 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
299 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
300 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
301 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
302 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
307 ISD, DstTy.getSimpleVT(),
315 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
316 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
317 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 },
318 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 },
319 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
320 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
321 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
322 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
323 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
324 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
325 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
326 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
327 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
328 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
329 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 },
330 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 },
331 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
332 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
333 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 },
334 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 }
340 ISD, DstTy.getSimpleVT(),
349 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
352 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 },
353 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 },
354 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
355 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
362 ISD, DstTy.getSimpleVT(),
387 int ISD = TLI->InstructionOpcodeToISD(Opcode);
389 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
392 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 },
393 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
394 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
395 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
396 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
397 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }
404 ISD, SelCondTy.getSimpleVT(),
431 { ISD::VECTOR_SHUFFLE, MVT::v2i32, 1 },
432 { ISD::VECTOR_SHUFFLE, MVT::v2f32, 1 },
433 { ISD::VECTOR_SHUFFLE, MVT::v2i64, 1 },
434 { ISD::VECTOR_SHUFFLE, MVT::v2f64, 1 },
436 { ISD::VECTOR_SHUFFLE, MVT::v4i32, 2 },
437 { ISD
438 { ISD::VECTOR_SHUFFLE, MVT::v8i16, 2 },
439 { ISD::VECTOR_SHUFFLE, MVT::v16i8, 2 }
445 ISD::VECTOR_SHUFFLE, LT.second);
