Lines Matching refs:ARM_AM
104 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
379 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
389 ARM_AM::ShiftOpc ShiftTy;
399 ARM_AM::ShiftOpc ShiftTy;
406 ARM_AM::ShiftOpc ShiftTy;
589 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
845 return ARM_AM::getSOImmVal(Value) != -1;
852 return ARM_AM::getSOImmVal(~Value) != -1;
860 return ARM_AM::getSOImmVal(Value) == -1 &&
861 ARM_AM::getSOImmVal(-Value) != -1;
868 return ARM_AM::getT2SOImmVal(Value) != -1;
875 return ARM_AM::getT2SOImmVal(~Value) != -1;
883 return ARM_AM::getT2SOImmVal(Value) == -1 &&
884 ARM_AM::getT2SOImmVal(-Value) != -1;
907 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
955 if (Memory.ShiftType != ARM_AM::no_shift) return false;
969 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
994 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1000 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1015 if (Memory.ShiftType == ARM_AM::no_shift)
1017 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1025 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1488 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1499 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1561 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1715 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1719 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1723 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1736 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1740 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1759 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1763 Val = ARM_AM::getAM3Opc(AddSub, Val);
1767 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1778 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1787 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1791 Val = ARM_AM::getAM3Opc(AddSub, Val);
1809 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1813 Val = ARM_AM::getAM5Opc(AddSub, Val);
1902 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1984 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1985 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2167 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2182 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2301 ARM_AM::ShiftOpc ShiftType,
2320 ARM_AM::ShiftOpc ShiftTy,
2403 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2404 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2427 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2433 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2558 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2559 .Case("asl", ARM_AM::lsl)
2560 .Case("lsl", ARM_AM::lsl)
2561 .Case("lsr", ARM_AM::lsr)
2562 .Case("asr", ARM_AM::asr)
2563 .Case("ror", ARM_AM::ror)
2564 .Case("rrx", ARM_AM::rrx)
2565 .Default(ARM_AM::no_shift);
2567 if (ShiftTy == ARM_AM::no_shift)
2583 if (ShiftTy == ARM_AM::rrx) {
2610 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2611 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2618 ShiftTy = ARM_AM::lsl;
2634 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3835 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3916 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4274 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4330 ARM_AM::no_shift, 0, Align,
4379 ARM_AM::no_shift, 0, 0,
4408 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4440 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4449 St = ARM_AM::lsl;
4451 St = ARM_AM::lsr;
4453 St = ARM_AM::asr;
4455 St = ARM_AM::ror;
4457 St = ARM_AM::rrx;
4464 if (St != ARM_AM::rrx) {
4484 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4485 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4489 St = ARM_AM::lsl;
4562 double RealVal = ARM_AM::getFPImmFloat(Val);
6866 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6868 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6869 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6870 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6871 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6900 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6902 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6903 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6904 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6905 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6906 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6908 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6931 ARM_AM::ShiftOpc ShiftTy;
6934 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6935 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6936 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6937 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6939 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6956 ARM_AM::ShiftOpc ShiftTy;
6959 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6960 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6961 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6962 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6968 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6970 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6984 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7066 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7075 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7324 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7326 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7328 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7349 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7350 if (SOpc == ARM_AM::rrx) return false;
7362 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7363 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
