Lines Matching refs:getOperand
4189 Inst.addOperand(Inst.getOperand(0));
5250 unsigned OpReg = Inst.getOperand(i).getReg();
5264 unsigned OpReg = Inst.getOperand(i).getReg();
5301 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5317 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5327 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5328 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5336 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5337 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5346 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5347 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5356 unsigned lsb = Inst.getOperand(2).getImm();
5357 unsigned widthm1 = Inst.getOperand(3).getImm();
5371 unsigned Rn = Inst.getOperand(0).getReg();
5393 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5448 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5721 if (Inst.getOperand(1).getReg() != ARM::PC ||
5722 Inst.getOperand(5).getReg() != 0)
5726 TmpInst.addOperand(Inst.getOperand(0));
5727 TmpInst.addOperand(Inst.getOperand(2));
5728 TmpInst.addOperand(Inst.getOperand(3));
5729 TmpInst.addOperand(Inst.getOperand(4));
5736 if (Inst.getOperand(1).getImm() > 0 &&
5737 Inst.getOperand(1).getImm() <= 0xff)
5763 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5764 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5765 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5766 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5767 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5768 TmpInst.addOperand(Inst.getOperand(1)); // lane
5769 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5770 TmpInst.addOperand(Inst.getOperand(6));
5785 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5786 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5787 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5788 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5789 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5790 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5792 TmpInst.addOperand(Inst.getOperand(1)); // lane
5793 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5794 TmpInst.addOperand(Inst.getOperand(6));
5809 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5810 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5811 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5812 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5813 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5814 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5816 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5818 TmpInst.addOperand(Inst.getOperand(1)); // lane
5819 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5820 TmpInst.addOperand(Inst.getOperand(6));
5835 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5836 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5837 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5838 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5839 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5840 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5842 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5844 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5846 TmpInst.addOperand(Inst.getOperand(1)); // lane
5847 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5848 TmpInst.addOperand(Inst.getOperand(6));
5861 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5862 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5863 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5865 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5866 TmpInst.addOperand(Inst.getOperand(1)); // lane
5867 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5868 TmpInst.addOperand(Inst.getOperand(5));
5883 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5884 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5885 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5887 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5890 TmpInst.addOperand(Inst.getOperand(1)); // lane
5891 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5892 TmpInst.addOperand(Inst.getOperand(5));
5907 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5908 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5909 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5911 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5912 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5914 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5916 TmpInst.addOperand(Inst.getOperand(1)); // lane
5917 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5918 TmpInst.addOperand(Inst.getOperand(5));
5933 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5934 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5935 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5937 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5938 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5940 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5942 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5944 TmpInst.addOperand(Inst.getOperand(1)); // lane
5945 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5946 TmpInst.addOperand(Inst.getOperand(5));
5959 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5960 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5961 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5962 TmpInst.addOperand(Inst.getOperand(1)); // lane
5963 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5964 TmpInst.addOperand(Inst.getOperand(5));
5979 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5980 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5981 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5982 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5984 TmpInst.addOperand(Inst.getOperand(1)); // lane
5985 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5986 TmpInst.addOperand(Inst.getOperand(5));
6001 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6002 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6003 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6004 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6006 getOperand(0).getReg() +
6008 TmpInst.addOperand(Inst.getOperand(1)); // lane
6009 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6010 TmpInst.addOperand(Inst.getOperand(5));
6025 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6026 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6027 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6028 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6030 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6032 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6034 TmpInst.addOperand(Inst.getOperand(1)); // lane
6035 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6036 TmpInst.addOperand(Inst.getOperand(5));
6050 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6051 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6052 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6053 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6054 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6055 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6056 TmpInst.addOperand(Inst.getOperand(1)); // lane
6057 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6058 TmpInst.addOperand(Inst.getOperand(6));
6073 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6074 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6076 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6077 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6078 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6079 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6080 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6081 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6083 TmpInst.addOperand(Inst.getOperand(1)); // lane
6084 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6085 TmpInst.addOperand(Inst.getOperand(6));
6100 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6101 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6103 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6105 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6106 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6107 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6108 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6109 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6110 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6112 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6114 TmpInst.addOperand(Inst.getOperand(1)); // lane
6115 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6116 TmpInst.addOperand(Inst.getOperand(6));
6131 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6132 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6134 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6136 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6138 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6139 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6140 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6141 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6142 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6143 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6145 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6147 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6149 TmpInst.addOperand(Inst.getOperand(1)); // lane
6150 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6151 TmpInst.addOperand(Inst.getOperand(6));
6164 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6165 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6166 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6167 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6169 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6170 TmpInst.addOperand(Inst.getOperand(1)); // lane
6171 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6172 TmpInst.addOperand(Inst.getOperand(5));
6187 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6188 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6190 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6191 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6192 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6194 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6195 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6197 TmpInst.addOperand(Inst.getOperand(1)); // lane
6198 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6199 TmpInst.addOperand(Inst.getOperand(5));
6214 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6215 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6217 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6219 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6220 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6221 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6223 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6224 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6226 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6228 TmpInst.addOperand(Inst.getOperand(1)); // lane
6229 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6230 TmpInst.addOperand(Inst.getOperand(5));
6245 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6246 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6248 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6250 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6252 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6253 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6254 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6256 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6257 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6259 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6261 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6263 TmpInst.addOperand(Inst.getOperand(1)); // lane
6264 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6265 TmpInst.addOperand(Inst.getOperand(5));
6278 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6279 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6280 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6281 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6282 TmpInst.addOperand(Inst.getOperand(1)); // lane
6283 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6284 TmpInst.addOperand(Inst.getOperand(5));
6299 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6300 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6302 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6303 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6304 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6305 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6307 TmpInst.addOperand(Inst.getOperand(1)); // lane
6308 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6309 TmpInst.addOperand(Inst.getOperand(5));
6324 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6325 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6327 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6329 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6330 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6331 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6332 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6334 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6336 TmpInst.addOperand(Inst.getOperand(1)); // lane
6337 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6338 TmpInst.addOperand(Inst.getOperand(5));
6353 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6354 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6356 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6358 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6360 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6361 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6362 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6363 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6365 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6367 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6369 TmpInst.addOperand(Inst.getOperand(1)); // lane
6370 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6371 TmpInst.addOperand(Inst.getOperand(5));
6386 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6387 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6389 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6391 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6392 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6393 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6394 TmpInst.addOperand(Inst.getOperand(4));
6408 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6409 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6411 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6413 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6414 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6415 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6417 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6418 TmpInst.addOperand(Inst.getOperand(4));
6432 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6433 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6435 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6437 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6438 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6439 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6440 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6441 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6442 TmpInst.addOperand(Inst.getOperand(5));
6457 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6458 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6460 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6462 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6463 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6464 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6465 TmpInst.addOperand(Inst.getOperand(4));
6479 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6480 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6482 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6484 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6485 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6486 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6488 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6489 TmpInst.addOperand(Inst.getOperand(4));
6503 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6504 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6506 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6508 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6509 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6510 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6511 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6512 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6513 TmpInst.addOperand(Inst.getOperand(5));
6528 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6529 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6531 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6533 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6535 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6536 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6537 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6538 TmpInst.addOperand(Inst.getOperand(4));
6552 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6553 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6555 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6557 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6559 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6560 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6561 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6563 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6564 TmpInst.addOperand(Inst.getOperand(4));
6578 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6579 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6581 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6583 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6585 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6586 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6587 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6588 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6589 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6590 TmpInst.addOperand(Inst.getOperand(5));
6605 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6606 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6608 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6610 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6612 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6613 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6614 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6615 TmpInst.addOperand(Inst.getOperand(4));
6629 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6630 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6632 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6634 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6636 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6637 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6638 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6640 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6641 TmpInst.addOperand(Inst.getOperand(4));
6655 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6656 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6658 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6660 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6662 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6663 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6664 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6665 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6666 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6667 TmpInst.addOperand(Inst.getOperand(5));
6682 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6683 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6684 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6685 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6687 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6689 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6690 TmpInst.addOperand(Inst.getOperand(4));
6704 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6705 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6706 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6708 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6709 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6711 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6713 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6714 TmpInst.addOperand(Inst.getOperand(4));
6728 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6729 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6730 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6731 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6732 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6733 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6735 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6737 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6738 TmpInst.addOperand(Inst.getOperand(5));
6753 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6754 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6755 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6756 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6758 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6760 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6762 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6763 TmpInst.addOperand(Inst.getOperand(4));
6777 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6778 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6779 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6781 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6782 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6784 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6786 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6788 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6789 TmpInst.addOperand(Inst.getOperand(4));
6803 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6804 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6805 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6806 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6807 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6808 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6810 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6812 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6814 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6815 TmpInst.addOperand(Inst.getOperand(5));
6824 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6825 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6826 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6839 TmpInst.addOperand(Inst.getOperand(0));
6840 TmpInst.addOperand(Inst.getOperand(5));
6841 TmpInst.addOperand(Inst.getOperand(1));
6842 TmpInst.addOperand(Inst.getOperand(2));
6843 TmpInst.addOperand(Inst.getOperand(3));
6844 TmpInst.addOperand(Inst.getOperand(4));
6858 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6859 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6860 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6861 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6866 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6874 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6878 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6879 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6880 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6881 TmpInst.addOperand(Inst.getOperand(5));
6894 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6895 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6900 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6908 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6911 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6915 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6918 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6919 TmpInst.addOperand(Inst.getOperand(4));
6942 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6943 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6944 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6946 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6947 TmpInst.addOperand(Inst.getOperand(4));
6948 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6965 unsigned Amt = Inst.getOperand(2).getImm();
6973 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6974 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6977 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6978 TmpInst.addOperand(Inst.getOperand(4));
6979 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6987 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6988 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6990 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6991 TmpInst.addOperand(Inst.getOperand(3));
6992 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7003 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7004 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7005 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7007 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7008 TmpInst.addOperand(Inst.getOperand(3));
7019 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7020 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7021 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7023 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7024 TmpInst.addOperand(Inst.getOperand(3));
7035 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7036 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7037 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7040 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7041 TmpInst.addOperand(Inst.getOperand(3));
7053 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7054 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7055 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7057 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7058 TmpInst.addOperand(Inst.getOperand(3));
7066 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7075 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7085 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7095 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7106 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7107 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7108 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7109 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7110 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7117 TmpInst.addOperand(Inst.getOperand(0));
7118 TmpInst.addOperand(Inst.getOperand(5));
7119 TmpInst.addOperand(Inst.getOperand(0));
7120 TmpInst.addOperand(Inst.getOperand(2));
7121 TmpInst.addOperand(Inst.getOperand(3));
7122 TmpInst.addOperand(Inst.getOperand(4));
7131 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7132 Inst.getOperand(5).getReg() != 0 ||
7138 TmpInst.addOperand(Inst.getOperand(0));
7139 TmpInst.addOperand(Inst.getOperand(0));
7140 TmpInst.addOperand(Inst.getOperand(2));
7141 TmpInst.addOperand(Inst.getOperand(3));
7142 TmpInst.addOperand(Inst.getOperand(4));
7149 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7158 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7165 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7172 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7179 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7189 unsigned Rn = Inst.getOperand(0).getReg();
7204 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7213 unsigned Rn = Inst.getOperand(0).getReg();
7251 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7252 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7253 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7254 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7255 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7261 TmpInst.addOperand(Inst.getOperand(0));
7262 TmpInst.addOperand(Inst.getOperand(4));
7263 TmpInst.addOperand(Inst.getOperand(1));
7264 TmpInst.addOperand(Inst.getOperand(2));
7265 TmpInst.addOperand(Inst.getOperand(3));
7274 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7275 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7276 Inst.getOperand(2).getImm() == ARMCC::AL &&
7277 Inst.getOperand(4).getReg() == ARM::CPSR &&
7282 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7283 TmpInst.addOperand(Inst.getOperand(0));
7284 TmpInst.addOperand(Inst.getOperand(1));
7285 TmpInst.addOperand(Inst.getOperand(2));
7286 TmpInst.addOperand(Inst.getOperand(3));
7298 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7299 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7300 Inst.getOperand(2).getImm() == 0 &&
7314 TmpInst.addOperand(Inst.getOperand(0));
7315 TmpInst.addOperand(Inst.getOperand(1));
7316 TmpInst.addOperand(Inst.getOperand(3));
7317 TmpInst.addOperand(Inst.getOperand(4));
7324 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7328 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7332 TmpInst.addOperand(Inst.getOperand(0));
7333 TmpInst.addOperand(Inst.getOperand(1));
7334 TmpInst.addOperand(Inst.getOperand(3));
7335 TmpInst.addOperand(Inst.getOperand(4));
7336 TmpInst.addOperand(Inst.getOperand(5));
7349 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7362 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7366 TmpInst.addOperand(Inst.getOperand(0));
7367 TmpInst.addOperand(Inst.getOperand(1));
7368 TmpInst.addOperand(Inst.getOperand(2));
7369 TmpInst.addOperand(Inst.getOperand(4));
7370 TmpInst.addOperand(Inst.getOperand(5));
7371 TmpInst.addOperand(Inst.getOperand(6));
7383 MCOperand &MO = Inst.getOperand(1);
7387 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7397 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7411 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7412 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7413 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7414 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7415 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7430 TmpInst.addOperand(Inst.getOperand(0));
7431 TmpInst.addOperand(Inst.getOperand(5));
7432 TmpInst.addOperand(Inst.getOperand(1));
7433 TmpInst.addOperand(Inst.getOperand(2));
7434 TmpInst.addOperand(Inst.getOperand(3));
7435 TmpInst.addOperand(Inst.getOperand(4));
7449 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7450 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7451 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7452 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7453 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7454 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7467 TmpInst.addOperand(Inst.getOperand(0));
7468 TmpInst.addOperand(Inst.getOperand(5));
7469 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7470 TmpInst.addOperand(Inst.getOperand(1));
7471 TmpInst.addOperand(Inst.getOperand(2));
7473 TmpInst.addOperand(Inst.getOperand(2));
7474 TmpInst.addOperand(Inst.getOperand(1));
7476 TmpInst.addOperand(Inst.getOperand(3));
7477 TmpInst.addOperand(Inst.getOperand(4));
7504 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7508 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7511 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7518 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7519 isARMLowRegister(Inst.getOperand(2).getReg()))
7523 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7524 isARMLowRegister(Inst.getOperand(1).getReg()))
