Lines Matching refs:ISD
54 ISD::ArgFlagsTy ArgFlags, CCState &State);
59 ISD::ArgFlagsTy ArgFlags, CCState &State);
64 ISD::ArgFlagsTy ArgFlags, CCState &State);
69 ISD::ArgFlagsTy ArgFlags, CCState &State);
74 ISD::ArgFlagsTy ArgFlags, CCState &State);
79 ISD::ArgFlagsTy ArgFlags, CCState &State);
84 ISD::ArgFlagsTy ArgFlags, CCState &State) {
133 ISD::ArgFlagsTy ArgFlags, CCState &State) {
171 ISD::ArgFlagsTy ArgFlags, CCState &State) {
189 ISD::ArgFlagsTy ArgFlags, CCState &State) {
214 ISD::ArgFlagsTy ArgFlags, CCState &State) {
245 ISD::ArgFlagsTy ArgFlags, CCState &State) {
261 ISD::ArgFlagsTy ArgFlags, CCState &State) {
287 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
297 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
303 const SmallVectorImpl<ISD::OutputArg> &Outs,
314 // Analyze return values of ISD::RET
344 /// LowerCallResult - Lower the result values of an ISD::CALL into the
348 /// ISD::CALL.
353 SmallVectorImpl<ISD::InputArg> &Ins,
386 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
388 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
460 ISD::ArgFlagsTy Flags = Outs[i].Flags;
470 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
473 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
476 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
483 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
510 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0],
604 if (Ptr->getOpcode() != ISD::ADD)
608 isInc = (Ptr->getOpcode() == ISD::ADD);
641 ISD::MemIndexedMode &AM,
650 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
666 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
680 case ISD::INLINEASM: {
753 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
755 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase,
778 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
814 SmallVectorImpl<ISD::InputArg> &Ins,
844 ISD::ArgFlagsTy Flags = Ins[i].Flags;
905 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0],
944 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i1, LHS, RHS, CC);
945 return DAG.getNode(ISD::SELECT, dl, SVT, Cond, TrueVal, FalseVal);
978 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1090 setOperationAction(ISD::SDIV, MVT::i32, Expand);
1092 setOperationAction(ISD::SREM, MVT::i32, Expand);
1095 setOperationAction(ISD::SDIV, MVT::i64, Expand);
1097 setOperationAction(ISD::SREM, MVT::i64, Expand);
1100 setOperationAction(ISD::UDIV, MVT::i32, Expand);
1103 setOperationAction(ISD::UDIV, MVT::i64, Expand);
1106 setOperationAction(ISD::UREM, MVT::i32, Expand);
1109 setOperationAction(ISD::UREM, MVT::i64, Expand);
1112 setOperationAction(ISD::FDIV, MVT::f32, Expand);
1115 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1117 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
1118 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1119 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1120 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1124 setOperationAction(ISD::FADD, MVT::f32, Legal);
1125 setOperationAction(ISD::FADD, MVT::f64, Legal);
1126 setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal);
1127 setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal);
1128 setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal);
1129 setCondCodeAction(ISD::SETUEQ, MVT::f32, Legal);
1130 setCondCodeAction(ISD::SETUEQ, MVT::f64, Legal);
1132 setCondCodeAction(ISD::SETOGE, MVT::f32, Legal);
1133 setCondCodeAction(ISD::SETOGE, MVT::f64, Legal);
1134 setCondCodeAction(ISD::SETUGE, MVT::f32, Legal);
1135 setCondCodeAction(ISD::SETUGE, MVT::f64, Legal);
1137 setCondCodeAction(ISD::SETOGT, MVT::f32, Legal);
1138 setCondCodeAction(ISD::SETOGT, MVT::f64, Legal);
1139 setCondCodeAction(ISD::SETUGT, MVT::f32, Legal);
1140 setCondCodeAction(ISD::SETUGT, MVT::f64, Legal);
1142 setCondCodeAction(ISD::SETOLE, MVT::f32, Legal);
1143 setCondCodeAction(ISD::SETOLE, MVT::f64, Legal);
1144 setCondCodeAction(ISD::SETOLT, MVT::f32, Legal);
1145 setCondCodeAction(ISD::SETOLT, MVT::f64, Legal);
1147 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
1148 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
1150 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1151 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1152 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1153 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1155 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1157 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1160 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1161 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1163 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1165 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1166 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1167 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1168 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1170 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1171 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1172 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1173 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1175 setOperationAction(ISD::FABS, MVT::f32, Legal);
1176 setOperationAction(ISD::FABS, MVT::f64, Expand);
1178 setOperationAction(ISD::FNEG, MVT::f32, Legal);
1179 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1183 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand);
1184 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
1186 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1187 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1211 setOperationAction(ISD::FADD, MVT::f64, Expand);
1214 setOperationAction(ISD::FADD, MVT::f32, Expand);
1217 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1220 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
1223 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
1226 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
1229 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
1232 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
1235 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
1238 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1241 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1244 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
1247 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
1250 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand);
1253 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand);
1256 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1259 setOperationAction(ISD::MUL, MVT::f32, Expand);
1262 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1267 setOperationAction(ISD::SUB, MVT::f64, Expand);
1270 setOperationAction(ISD::SUB, MVT::f32, Expand);
1273 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1276 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
1279 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
1282 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
1285 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
1287 setOperationAction(ISD::FABS, MVT::f32, Expand);
1288 setOperationAction(ISD::FABS, MVT::f64, Expand);
1289 setOperationAction(ISD::FNEG, MVT::f32, Expand);
1290 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1294 setOperationAction(ISD::SREM, MVT::i32, Expand);
1296 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
1297 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
1298 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1299 setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal);
1301 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal);
1302 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal);
1303 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1304 setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal);
1306 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1309 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
1311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
1316 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1317 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1318 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1320 setOperationAction(ISD::TRUNCATE, MVT::i64, Expand);
1323 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1326 setOperationAction(ISD::UREM, MVT::i32, Expand);
1327 setOperationAction(ISD::SREM, MVT::i32, Expand);
1328 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1329 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1330 setOperationAction(ISD::SREM, MVT::i64, Expand);
1331 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1332 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1334 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1337 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1338 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1345 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1346 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1348 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
1349 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
1350 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
1355 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1356 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1360 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
1364 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1366 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1368 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1373 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
1374 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
1378 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
1379 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1381 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1382 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1383 setOperationAction(ISD::FREM , MVT::f64, Expand);
1384 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1385 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1386 setOperationAction(ISD::FREM , MVT::f32, Expand);
1387 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1388 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1395 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1396 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1397 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1398 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1399 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1400 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1401 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1402 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1403 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1404 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1405 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1406 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1407 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1408 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1409 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1410 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1412 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1413 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
1414 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1415 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1416 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1417 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1418 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1419 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1420 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1421 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1422 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1423 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1424 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1425 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1426 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1427 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1428 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1430 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1431 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1432 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1434 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1435 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1437 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1438 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1440 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
1441 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
1442 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
1443 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
1445 setOperationAction(ISD::EH_RETURN, MVT::Other, Expand);
1456 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1459 setOperationAction(ISD::VAARG , MVT::Other, Expand);
1460 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1461 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1462 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1463 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1466 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1467 setOperationAction(ISD::INLINEASM , MVT::Other, Custom);
1524 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1526 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
1527 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
1528 case ISD::GlobalTLSAddress:
1530 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
1531 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
1532 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
1533 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
1534 case ISD::VASTART: return LowerVASTART(Op, DAG);
1535 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1537 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
1538 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1539 case ISD::SELECT: return Op;
1540 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1541 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
1648 const SmallVectorImpl<ISD::OutputArg> &Outs,
1650 const SmallVectorImpl<ISD::InputArg> &Ins,
