Lines Matching refs:ISD
103 return DAG.getNode(ISD::ADD, DL, Ty,
120 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
139 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
211 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
212 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
213 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
216 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
223 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
226 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
227 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
228 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
229 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
230 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
231 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
232 setOperationAction(ISD::SELECT, MVT::f32, Custom);
233 setOperationAction(ISD::SELECT, MVT::f64, Custom);
234 setOperationAction(ISD::SELECT, MVT::i32, Custom);
235 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
236 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
237 setOperationAction(ISD::SETCC, MVT::f32, Custom);
238 setOperationAction(ISD::SETCC, MVT::f64, Custom);
239 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
240 setOperationAction(ISD::VASTART, MVT::Other, Custom);
241 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
242 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
245 setOperationAction(ISD::FABS, MVT::f32, Custom);
246 setOperationAction(ISD::FABS, MVT::f64, Custom);
250 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
251 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
252 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
253 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
254 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
255 setOperationAction(ISD::SELECT, MVT::i64, Custom);
256 setOperationAction(ISD::LOAD, MVT::i64, Custom);
257 setOperationAction(ISD::STORE, MVT::i64, Custom);
261 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
262 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
263 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
266 setOperationAction(ISD::ADD, MVT::i32, Custom);
268 setOperationAction(ISD::ADD, MVT::i64, Custom);
270 setOperationAction(ISD::SDIV, MVT::i32, Expand);
271 setOperationAction(ISD::SREM, MVT::i32, Expand);
272 setOperationAction(ISD::UDIV, MVT::i32, Expand);
273 setOperationAction(ISD::UREM, MVT::i32, Expand);
274 setOperationAction(ISD::SDIV, MVT::i64, Expand);
275 setOperationAction(ISD::SREM, MVT::i64, Expand);
276 setOperationAction(ISD::UDIV, MVT::i64, Expand);
277 setOperationAction(ISD::UREM, MVT::i64, Expand);
280 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
281 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
282 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
283 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
284 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
285 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
286 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
287 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
288 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
289 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
290 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
291 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
292 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
293 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
294 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
295 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
296 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
297 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
298 setOperationAction(ISD::ROTL, MVT::i32, Expand);
299 setOperationAction(ISD::ROTL, MVT::i64, Expand);
300 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
301 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
304 setOperationAction(ISD::ROTR, MVT::i32, Expand);
307 setOperationAction(ISD::ROTR, MVT::i64, Expand);
309 setOperationAction(ISD::FSIN, MVT::f32, Expand);
310 setOperationAction(ISD::FSIN, MVT::f64, Expand);
311 setOperationAction(ISD::FCOS, MVT::f32, Expand);
312 setOperationAction(ISD::FCOS, MVT::f64, Expand);
313 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
314 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
315 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
316 setOperationAction(ISD::FPOW, MVT::f32, Expand);
317 setOperationAction(ISD::FPOW, MVT::f64, Expand);
318 setOperationAction(ISD::FLOG, MVT::f32, Expand);
319 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
320 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
321 setOperationAction(ISD::FEXP, MVT::f32, Expand);
322 setOperationAction(ISD::FMA, MVT::f32, Expand);
323 setOperationAction(ISD::FMA, MVT::f64, Expand);
324 setOperationAction(ISD::FREM, MVT::f32, Expand);
325 setOperationAction(ISD::FREM, MVT::f64, Expand);
328 setOperationAction(ISD::FNEG, MVT::f32, Expand);
329 setOperationAction(ISD::FNEG, MVT::f64, Expand);
332 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
333 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
334 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
335 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
337 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
339 setOperationAction(ISD::VAARG, MVT::Other, Expand);
340 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
341 setOperationAction(ISD::VAEND, MVT::Other, Expand);
343 setOperationAction(ISD
344 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
347 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
348 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
350 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
351 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
352 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
353 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
358 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
359 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
363 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
364 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
368 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
369 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
373 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom);
374 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom);
375 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom);
379 setTargetDAGCombine(ISD::ADDE);
380 setTargetDAGCombine(ISD::SUBE);
381 setTargetDAGCombine(ISD::SDIVREM);
382 setTargetDAGCombine(ISD::UDIVREM);
383 setTargetDAGCombine(ISD::SELECT);
384 setTargetDAGCombine(ISD::AND);
385 setTargetDAGCombine(ISD::OR);
386 setTargetDAGCombine(ISD::ADD);
424 if (ADDCNode->getOpcode() != ISD::ADDC)
437 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
459 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
497 if (SUBCNode->getOpcode() != ISD::SUBC)
510 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
532 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
592 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
620 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
623 case ISD::SETEQ:
624 case ISD::SETOEQ: return Mips::FCOND_OEQ;
625 case ISD::SETUNE: return Mips::FCOND_UNE;
626 case ISD::SETLT:
627 case ISD::SETOLT: return Mips::FCOND_OLT;
628 case ISD::SETGT:
629 case ISD::SETOGT: return Mips::FCOND_OGT;
630 case ISD::SETLE:
631 case ISD::SETOLE: return Mips::FCOND_OLE;
632 case ISD::SETGE:
633 case ISD::SETOGE: return Mips::FCOND_OGE;
634 case ISD::SETULT: return Mips::FCOND_ULT;
635 case ISD::SETULE: return Mips::FCOND_ULE;
636 case ISD::SETUGT: return Mips::FCOND_UGT;
637 case ISD::SETUGE: return Mips::FCOND_UGE;
638 case ISD::SETUO: return Mips::FCOND_UN;
639 case ISD::SETO: return Mips::FCOND_OR;
640 case ISD::SETNE:
641 case ISD::SETONE: return Mips::FCOND_ONE;
642 case ISD::SETUEQ: return Mips::FCOND_UEQ;
662 if (Op.getOpcode() != ISD::SETCC)
675 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
700 if ((SetCC.getOpcode() != ISD::SETCC) ||
716 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
720 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
722 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
738 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
780 if (And0.getOpcode() != ISD::AND)
788 if (And1.getOpcode() != ISD::AND)
800 if (Shl.getOpcode() != ISD::SHL)
829 if (Add.getOpcode() != ISD::ADD)
835 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
841 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
843 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
853 case ISD::ADDE:
855 case ISD::SUBE:
857 case ISD::SDIVREM:
858 case ISD::UDIVREM:
860 case ISD::SELECT:
862 case ISD::AND:
864 case ISD::OR:
866 case ISD::ADD:
898 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
899 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
900 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
901 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
902 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
903 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
904 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
905 case ISD::SELECT: return lowerSELECT(Op, DAG);
906 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
907 case ISD::SETCC: return lowerSETCC(Op, DAG);
908 case ISD::VASTART: return lowerVASTART(Op, DAG);
909 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
910 case ISD::FABS: return lowerFABS(Op, DAG);
911 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
912 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
913 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
914 case ISD::MEMBARRIER: return lowerMEMBARRIER(Op, DAG);
915 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
916 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
917 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
918 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
919 case ISD::LOAD: return lowerLOAD(Op, DAG);
920 case ISD::STORE: return lowerSTORE(Op, DAG);
921 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
922 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
923 case ISD::ADD: return lowerADD(Op, DAG);
1545 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1547 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1550 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1559 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1563 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1608 SDValue Cond = DAG.getNode(ISD::SETCC, DL, getSetCCResultType(Ty),
1612 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1645 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode);
1722 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1723 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1745 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1749 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1772 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
1806 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1810 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1825 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1826 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1827 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1828 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1829 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1833 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1848 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1849 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1858 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1860 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1864 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1872 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1873 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1874 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1878 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1880 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1882 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1884 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1885 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
1903 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1913 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1914 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1918 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1930 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1938 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1939 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1942 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2044 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2046 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
2048 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
2050 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
2051 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2052 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2053 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2055 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2057 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
2082 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2084 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2086 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2087 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2088 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2089 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2091 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2093 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2095 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2096 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2113 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2133 ISD::LoadExtType ExtType = LD->getExtensionType();
2143 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2162 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2163 (ExtType == ISD::EXTLOAD))
2166 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2177 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2178 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2191 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2256 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2259 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
2284 SDValue Out = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, OutLo, OutHi);
2382 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2385 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2398 return DAG.getNode(ISD::ADD, Op->getDebugLoc(), ValTy, InArgsAddr,
2423 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2523 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
2587 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2589 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2647 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2670 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2687 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2690 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2693 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2707 // emit ISD::STORE whichs stores the
2716 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2783 const SmallVectorImpl<ISD::InputArg> &Ins,
2805 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val);
2822 const SmallVectorImpl<ISD::InputArg> &Ins,
2856 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2898 Opcode = ISD::AssertSext;
2900 Opcode = ISD::AssertZext;
2904 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue);
2912 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
2952 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
2962 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
2976 const SmallVectorImpl<ISD::OutputArg> &Outs,
2987 const SmallVectorImpl<ISD::OutputArg> &Outs,
3014 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val);
3382 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args,
3393 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3420 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args,
3428 ISD::ArgFlagsTy ArgFlags = Args[I].Flags;
3463 ISD::ArgFlagsTy Flags = RetVals[I].Flags;
3477 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat,
3483 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat,
3492 ISD::ArgFlagsTy ArgFlags) {
3579 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
3611 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3627 const ISD::ArgFlagsTy &Flags, bool isLittle) const {
3641 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3669 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3672 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr,
3685 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3689 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3706 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3708 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
