Lines Matching full:x86
1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
10 // This file is part of the X86 Disassembler.
56 namespace X86 {
159 #define ENTRY(x) X86::x,
341 // By default sign-extend all X86 immediates based on their encoding.
349 // Special case those X86 instructions that use the imm8 as a set of
351 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
352 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
353 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
354 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
355 Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
356 Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
357 Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
358 Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
359 Opcode != X86::VINSERTPSrr)
378 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
381 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
444 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
489 baseReg = MCOperand::CreateReg(X86::x); break;
504 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm ||
505 Opcode == X86::VGATHERDPDYrm ||
506 Opcode == X86::VGATHERQPDrm ||
507 Opcode == X86::VGATHERDPSrm ||
508 Opcode == X86::VGATHERQPSrm ||
509 Opcode == X86::VPGATHERDQrm ||
510 Opcode == X86::VPGATHERDQYrm ||
511 Opcode == X86::VPGATHERQQrm ||
512 Opcode == X86::VPGATHERDDrm ||
513 Opcode == X86::VPGATHERQDrm);
514 bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm ||
515 Opcode == X86::VGATHERDPSYrm ||
516 Opcode == X86::VGATHERQPSYrm ||
517 Opcode == X86::VPGATHERQQYrm ||
518 Opcode == X86::VPGATHERDDYrm ||
519 Opcode == X86::VPGATHERQDYrm);
535 indexReg = MCOperand::CreateReg(X86::x); break;
560 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
568 baseReg = MCOperand::CreateReg(X86::BX);
569 indexReg = MCOperand::CreateReg(X86::SI);
572 baseReg = MCOperand::CreateReg(X86::BX);
573 indexReg = MCOperand::CreateReg(X86::DI);
576 baseReg = MCOperand::CreateReg(X86::BP);
577 indexReg = MCOperand::CreateReg(X86::SI);
580 baseReg = MCOperand::CreateReg(X86::BP);
581 indexReg = MCOperand::CreateReg(X86::DI);
595 baseReg = MCOperand::CreateReg(X86::x); break;
614 X86::CS,
615 X86::SS,
616 X86::DS,
617 X86::ES,
618 X86::FS,
619 X86::GS
701 mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
