Lines Matching full:x86
1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
34 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
35 cl::desc("Disable relaxation of arithmetic instruction for X86"));
47 case X86::reloc_riprel_4byte:
48 case X86::reloc_riprel_4byte_movq_load:
49 case X86::reloc_signed_4byte:
50 case X86::reloc_global_offset_table:
75 return X86::NumTargetFixupKinds;
79 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
130 case X86::JAE_1: return X86::JAE_4;
131 case X86::JA_1: return X86::JA_4;
132 case X86::JBE_1: return X86::JBE_4;
133 case X86::JB_1: return X86::JB_4;
134 case X86::JE_1: return X86::JE_4;
135 case X86::JGE_1: return X86::JGE_4;
136 case X86::JG_1: return X86::JG_4;
137 case X86::JLE_1: return X86::JLE_4;
138 case X86::JL_1: return X86::JL_4;
139 case X86::JMP_1: return X86::JMP_4;
140 case X86::JNE_1: return X86::JNE_4;
141 case X86::JNO_1: return X86::JNO_4;
142 case X86::JNP_1: return X86::JNP_4;
143 case X86::JNS_1: return X86::JNS_4;
144 case X86::JO_1: return X86::JO_4;
145 case X86::JP_1: return X86::JP_4;
146 case X86::JS_1: return X86::JS_4;
156 case X86::IMUL16rri8: return X86::IMUL16rri;
157 case X86::IMUL16rmi8: return X86::IMUL16rmi;
158 case X86::IMUL32rri8: return X86::IMUL32rri;
159 case X86::IMUL32rmi8: return X86::IMUL32rmi;
160 case X86::IMUL64rri8: return X86::IMUL64rri32;
161 case X86::IMUL64rmi8: return X86::IMUL64rmi32;
164 case X86::AND16ri8: return X86::AND16ri;
165 case X86::AND16mi8: return X86::AND16mi;
166 case X86::AND32ri8: return X86::AND32ri;
167 case X86::AND32mi8: return X86::AND32mi;
168 case X86::AND64ri8: return X86::AND64ri32;
169 case X86::AND64mi8: return X86::AND64mi32;
172 case X86::OR16ri8: return X86::OR16ri;
173 case X86::OR16mi8: return X86::OR16mi;
174 case X86::OR32ri8: return X86::OR32ri;
175 case X86::OR32mi8: return X86::OR32mi;
176 case X86::OR64ri8: return X86::OR64ri32;
177 case X86::OR64mi8: return X86::OR64mi32;
180 case X86::XOR16ri8: return X86::XOR16ri;
181 case X86::XOR16mi8: return X86::XOR16mi;
182 case X86::XOR32ri8: return X86::XOR32ri;
183 case X86::XOR32mi8: return X86::XOR32mi;
184 case X86::XOR64ri8: return X86::XOR64ri32;
185 case X86::XOR64mi8: return X86::XOR64mi32;
188 case X86::ADD16ri8: return X86::ADD16ri;
189 case X86::ADD16mi8: return X86::ADD16mi;
190 case X86::ADD32ri8: return X86::ADD32ri;
191 case X86::ADD32mi8: return X86::ADD32mi;
192 case X86::ADD64ri8: return X86::ADD64ri32;
193 case X86::ADD64mi8: return X86::ADD64mi32;
196 case X86::SUB16ri8: return X86::SUB16ri;
197 case X86::SUB16mi8: return X86::SUB16mi;
198 case X86::SUB32ri8: return X86::SUB32ri;
199 case X86::SUB32mi8: return X86::SUB32mi;
200 case X86::SUB64ri8: return X86::SUB64ri32;
201 case X86::SUB64mi8: return X86::SUB64mi32;
204 case X86::CMP16ri8: return X86::CMP16ri;
205 case X86::CMP16mi8: return X86::CMP16mi;
206 case X86::CMP32ri8: return X86::CMP32ri;
207 case X86::CMP32mi8: return X86::CMP32mi;
208 case X86::CMP64ri8: return X86::CMP64ri32;
209 case X86::CMP64mi8: return X86::CMP64mi32;
212 case X86::PUSHi8: return X86::PUSHi32;
213 case X86::PUSHi16: return X86::PUSHi32;
214 case X86::PUSH64i8: return X86::PUSH64i32;
215 case X86::PUSH64i16: return X86::PUSH64i32;
247 if (Op.isReg() && Op.getReg() == X86::RIP)
267 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
