Lines Matching full:x86
1 //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
10 // This file defines the X86-specific support for the FastISel class. Much
16 #include "X86.h"
48 /// RegInfo - X86 register info.
168 // We only handle legal types. For example, on x86-32 the instruction
169 // selector contains all of the 64-bit instructions from x86-64,
189 Opc = X86::MOV8rm;
190 RC = &X86::GR8RegClass;
193 Opc = X86::MOV16rm;
194 RC = &X86::GR16RegClass;
197 Opc = X86::MOV32rm;
198 RC = &X86::GR32RegClass;
201 // Must be in x86-64 mode.
202 Opc = X86::MOV64rm;
203 RC = &X86::GR64RegClass;
207 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
208 RC = &X86::FR32RegClass;
210 Opc = X86::LD_Fp32m;
211 RC = &X86::RFP32RegClass;
216 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
217 RC = &X86::FR64RegClass;
219 Opc = X86::LD_Fp64m;
220 RC = &X86::RFP64RegClass;
247 unsigned AndResult = createResultReg(&X86::GR8RegClass);
249 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
253 case MVT::i8: Opc = X86::MOV8mr; break;
254 case MVT::i16: Opc = X86::MOV16mr; break;
255 case MVT::i32: Opc = X86::MOV32mr; break;
256 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode.
259 (Subtarget->hasAVX() ? X86::VMOVSSmr : X86::MOVSSmr) : X86::ST_Fp32m;
263 (Subtarget->hasAVX() ? X86::VMOVSDmr : X86::MOVSDmr) : X86::ST_Fp64m;
266 Opc = X86::MOVAPSmr;
269 Opc = X86::MOVAPDmr;
275 Opc = X86::MOVDQAmr;
297 case MVT::i8: Opc = X86::MOV8mi; break;
298 case MVT::i16: Opc = X86::MOV16mi; break;
299 case MVT::i32: Opc = X86::MOV32mi; break;
303 Opc = X86::MOV64mi32;
527 AM.Base.Reg = X86::RIP;
552 Opc = X86::MOV64rm;
553 RC = &X86::GR64RegClass;
556 StubAM.Base.Reg = X86::RIP;
558 Opc = X86::MOV32rm;
559 RC = &X86::GR32RegClass;
659 AM.Base.Reg = X86::RIP;
775 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
789 assert(DstVT == MVT::i32 && "X86 should always ext to i32");
816 // The x86-64 ABI for returning structs by value requires that we copy
825 X86::RAX).addReg(Reg);
826 RetRegs.push_back(X86::RAX);
831 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
867 case MVT::i8: return X86::CMP8rr;
868 case MVT::i16: return X86::CMP16rr;
869 case MVT::i32: return X86::CMP32rr;
870 case MVT::i64: return X86::CMP64rr;
872 return X86ScalarSSEf32 ? (HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) : 0;
874 return X86ScalarSSEf64 ? (HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) : 0;
885 case MVT::i8: return X86::CMP8ri;
886 case MVT::i16: return X86::CMP16ri;
887 case MVT::i32: return X86::CMP32ri;
892 return X86::CMP64ri32;
937 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
945 unsigned EReg = createResultReg(&X86::GR8RegClass);
946 unsigned NPReg = createResultReg(&X86::GR8RegClass);
947 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
949 TII.get(X86::SETNPr), NPReg);
951 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
959 unsigned NEReg = createResultReg(&X86::GR8RegClass);
960 unsigned PReg = createResultReg(&X86::GR8RegClass);
961 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETNEr), NEReg);
962 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETPr), PReg);
963 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::OR8rr),ResultReg)
968 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
969 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
970 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break;
971 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break;
972 X86::SETNEr; break;
973 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break;
974 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break;
975 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
976 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break;
977 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break;
978 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
979 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
981 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break;
982 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break;
983 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break;
984 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break;
985 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break;
986 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break;
987 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break;
988 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break;
989 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break;
990 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break;
1060 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA"
1067 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1068 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1069 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1070 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break;
1071 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break;
1072 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1073 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break;
1074 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break;
1075 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1076 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break;
1077 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break;
1078 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1079 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1081 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break;
1082 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break;
1083 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break;
1084 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break;
1085 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break;
1086 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break;
1087 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break;
1088 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break;
1089 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break;
1090 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break;
1107 // X86 requires a second branch to handle UNE (and OEQ,
1109 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
1126 case MVT::i8: TestOpc = X86::TEST8ri; break;
1127 case MVT::i16: TestOpc = X86::TEST16ri; break;
1128 case MVT::i32: TestOpc = X86::TEST32ri; break;
1129 case MVT::i64: TestOpc = X86::TEST64ri32; break;
1137 unsigned JmpOpc = X86::JNE_4;
1140 JmpOpc = X86::JE_4;
1158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8ri))
1160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1171 CReg = X86::CL;
1172 RC = &X86::GR8RegClass;
1174 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1175 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1176 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1180 CReg = X86::CX;
1181 RC = &X86::GR16RegClass;
1183 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1184 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1185 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1189 CReg = X86::ECX;
1190 RC = &X86::GR32RegClass;
1192 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1193 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1194 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1198 CReg = X86::RCX;
1199 RC = &X86::GR64RegClass;
1201 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1202 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1203 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1222 // The shift instruction uses X86::CL. If we defined a super-register
1223 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1224 if (CReg != X86::CL)
1226 TII.get(TargetOpcode::KILL), X86::CL)
1247 Opc = X86::CMOVE16rr;
1248 RC = &X86::GR16RegClass;
1250 Opc = X86::CMOVE32rr;
1251 RC = &X86::GR32RegClass;
1253 Opc = X86::CMOVE64rr;
1254 RC = &X86::GR64RegClass;
1266 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1283 unsigned ResultReg = createResultReg(&X86::FR64RegClass);
1285 TII.get(X86::CVTSS2SDrr), ResultReg)
1302 unsigned ResultReg = createResultReg(&X86::FR32RegClass);
1304 TII.get(X86::CVTSD2SSrr), ResultReg)
1337 // If we're on x86-32; we can't extract an i8 from a general register.
1340 (const TargetRegisterClass*)&X86::GR16_ABCDRegClass :
1341 (const TargetRegisterClass*)&X86::GR32_ABCDRegClass;
1351 X86::sub_8bit);
1474 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
1502 OpC = X86::ADD32rr;
1504 OpC = X86::ADD64rr;
1514 unsigned Opc = X86::SETBr;
1516 Opc = X86::SETOr;
1572 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
1575 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
1657 // x86-32. Special handling for x86-64 is implemented.
1662 if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg,
1734 // calling conventions on x86.
1899 X86::EBX).addReg(Base);
1905 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1906 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1909 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::MOV8ri),
1910 X86::AL).addImm(NumXMMRegs);
1919 CallOpc = X86::CALL64r;
1921 CallOpc = X86::CALL32r;
1930 CallOpc = X86::CALL64pcrel32;
1932 CallOpc = X86::CALLpcrel32;
1937 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1969 MIB.addReg(X86::EBX, RegState::Implicit);
1972 MIB.addReg(X86::AL, RegState::Implicit);
2021 if ((RVLocs[i].getLocReg() == X86::ST0 ||
2022 RVLocs[i].getLocReg() == X86::ST1)) {
2025 CopyReg = createResultReg(&X86::RFP80RegClass);
2027 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL),
2040 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
2046 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
2126 Opc = X86::MOV8rm;
2127 RC = &X86::GR8RegClass;
2130 Opc = X86::MOV16rm;
2131 RC = &X86::GR16RegClass;
2134 Opc = X86::MOV32rm;
2135 RC = &X86::GR32RegClass;
2138 // Must be in x86-64 mode.
2139 Opc = X86::MOV64rm;
2140 RC = &X86::GR64RegClass;
2144 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
2145 RC = &X86::FR32RegClass;
2147 Opc = X86::LD_Fp32m;
2148 RC = &X86::RFP32RegClass;
2153 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
2154 RC = &X86::FR64RegClass;
2156 Opc = X86::LD_Fp64m;
2157 RC = &X86::RFP64RegClass;
2175 Opc = TLI.getPointerTy() == MVT::i32 ? X86::LEA32r : X86::LEA64r;
2191 // x86-32 PIC requires a PIC base register for constant pools.
2202 PICBase = X86::RIP;
2229 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
2249 Opc = X86::FsFLD0SS;
2250 RC = &X86::FR32RegClass;
2252 Opc = X86::LD_Fp032;
2253 RC = &X86::RFP32RegClass;
2258 Opc = X86::FsFLD0SD;
2259 RC = &X86::FR64RegClass;
2261 Opc = X86::LD_Fp064;
2262 RC = &X86::RFP64RegClass;
2305 FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo,
