Lines Matching defs:Opc
107 unsigned Opc = MBBI->getOpcode();
108 switch (Opc) {
152 unsigned Opc;
154 Opc = getLEArOpcode(IsLP64);
156 Opc = isSub
171 Opc = isSub
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
209 unsigned Opc = PI->getOpcode();
210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
239 unsigned Opc = NI->getOpcode();
240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
271 unsigned Opc = PI->getOpcode();
274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
526 unsigned Opc = MI.getOpcode();
527 if (Opc == X86::PROLOG_LABEL) continue;
533 if (Opc == PushInstr) {
540 } else if (Opc == MoveInstr) {
551 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
552 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) {
952 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
953 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1062 unsigned Opc = PI->getOpcode();
1064 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1086 unsigned Opc = getLEArOpcode(IsLP64);
1087 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1090 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
1091 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1258 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1270 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1319 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1328 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1800 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1801 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1821 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1822 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
