Lines Matching full:x86
1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
61 return X86::SUB64ri8;
62 return X86::SUB64ri32;
65 return X86::SUB32ri8;
66 return X86::SUB32ri;
73 return X86::ADD64ri8;
74 return X86::ADD64ri32;
77 return X86::ADD32ri8;
78 return X86::ADD32ri;
83 return IsLP64 ? X86::LEA64r : X86::LEA32r;
99 X86::EAX, X86::EDX, X86::ECX, 0
103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
104 X86::R8, X86::R9, X86::R10, X86::R11, 0
110 case X86::RET:
111 case X86::RETI:
112 case X86::TCRETURNdi:
113 case X86::TCRETURNri:
114 case X86::TCRETURNmi:
115 case X86::TCRETURNdi64:
116 case X86::TCRETURNri64:
117 case X86::TCRETURNmi64:
118 case X86::EH_RETURN:
119 case X86::EH_RETURN64: {
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
173 : (Is64Bit ? X86::POP64r : X86::POP32r);
210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL)
402 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
405 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
470 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
473 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
509 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
511 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
527 if (Opc == X86::PROLOG_LABEL) continue;
551 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
552 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) {
636 for (MachineRegisterInfo::reg_iterator ri = MRI.reg_begin(X86::EFLAGS),
690 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
759 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
766 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
788 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
795 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
817 (MBBI->getOpcode() == X86::PUSH32r ||
818 MBBI->getOpcode() == X86::PUSH64r)) {
826 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
849 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
902 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
903 .addReg(X86::EAX, RegState::Kill)
910 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
916 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
922 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
925 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
936 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
937 X86::EAX),
952 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
961 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
1010 case X86::RET:
1011 case X86::RETI:
1012 case X86::TCRETURNdi:
1013 case X86::TCRETURNri:
1014 case X86::TCRETURNmi:
1015 case X86::TCRETURNdi64:
1016 case X86::TCRETURNri64:
1017 case X86::TCRETURNmi64:
1018 case X86::EH_RETURN:
1019 case X86::EH_RETURN64:
1054 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1064 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1090 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
1101 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1106 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1108 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1109 RetOpcode == X86::TCRETURNmi ||
1110 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1111 RetOpcode == X86::TCRETURNmi64) {
1112 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1137 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1139 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1140 ? X86::TAILJMPd : X86::TAILJMPd64));
1149 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1151 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1152 ? X86::TAILJMPm : X86::TAILJMPm64));
1155 } else if (RetOpcode == X86::TCRETURNri64) {
1156 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1159 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1168 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1258 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1261 if (!X86::GR64RegClass.contains(Reg) &&
1262 !X86::GR32RegClass.contains(Reg))
1276 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1281 if (X86::GR64RegClass.contains(Reg) ||
1282 X86::GR32RegClass.contains(Reg))
1309 if (X86::GR64RegClass.contains(Reg) ||
1310 X86::GR32RegClass.contains(Reg))
1319 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1322 if (!X86::GR64RegClass.contains(Reg) &&
1323 !X86::GR32RegClass.contains(Reg))
1400 return Primary ? X86::R14 : X86::R13;
1402 return Primary ? X86::EBX : X86::EDI;
1406 return Primary ? X86::R11 : X86::R12;
1415 return Primary ? X86::EAX : X86::ECX;
1418 return Primary ? X86::EDX : X86::EAX;
1419 return Primary ? X86::ECX : X86::EAX;
1465 allocMBB->addLiveIn(X86::R10);
1482 TlsReg = X86::FS;
1485 TlsReg = X86::GS;
1488 TlsReg = X86::FS;
1495 ScratchReg = X86::RSP;
1497 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1500 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1504 TlsReg = X86::GS;
1507 TlsReg = X86::GS;
1510 TlsReg = X86::FS;
1519 ScratchReg = X86::ESP;
1521 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1525 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1549 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1552 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1554 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1561 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1567 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1576 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1578 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1580 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1582 MF.getRegInfo().setPhysRegUsed(X86::R10);
1583 MF.getRegInfo().setPhysRegUsed(X86::R11);
1585 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1587 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1593 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1596 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1600 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1602 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1712 SPReg = X86::RSP;
1713 PReg = X86::RBP;
1714 LEAop = X86::LEA64r;
1715 CMPop = X86::CMP64rm;
1716 CALLop = X86::CALL64pcrel32;
1719 SPReg = X86::ESP;
1720 PReg = X86::EBP;
1721 LEAop = X86::LEA32r;
1722 CMPop = X86::CMP32rm;
1723 CALLop = X86::CALLpcrel32;
1737 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1746 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
