Lines Matching refs:Is64Bit
92 bool Is64Bit) {
132 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
148 bool Is64Bit, bool IsLP64, bool UseLEA,
165 if (ThisVal == (Is64Bit ? 8 : 4)) {
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
173 : (Is64Bit ? X86::POP64r : X86::POP32r);
388 unsigned RegCount, bool Is64Bit) {
407 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
468 bool Is64Bit) {
475 const uint16_t *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs);
501 bool Is64Bit = STI.is64Bit();
507 unsigned OffsetSize = (Is64Bit ? 8 : 4);
509 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
511 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
512 unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
513 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
515 unsigned StackDivide = (Is64Bit ? 8 : 4);
580 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
618 Is64Bit);
662 bool Is64Bit = STI.is64Bit();
695 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
759 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
788 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
849 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
881 if (Is64Bit) {
899 assert(!Is64Bit && "EAX is livein in x64 case!");
907 if (Is64Bit) {
922 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
931 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
943 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
952 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
999 bool Is64Bit = STI.is64Bit();
1054 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1090 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
1096 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
1106 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1132 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
1176 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
1250 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
1258 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1319 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1394 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1399 if (Is64Bit)
1405 if (Is64Bit)
1432 bool Is64Bit = STI.is64Bit();
1436 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1452 if (Is64Bit)
1480 if (Is64Bit) {
1534 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1538 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1571 if (Is64Bit) {
1592 if (Is64Bit)
1633 const bool Is64Bit = STI.is64Bit();
1637 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1711 if (Is64Bit) {
1727 ScratchReg = GetScratchRegister(Is64Bit, MF, true);
