Lines Matching defs:eax
563 setExceptionPointerRegister(X86::EAX);
1681 // the sret argument into %rax/%eax (depending on ABI) for the return.
1683 // so now we copy the value out and into %rax/%eax.
1693 unsigned RetValReg = Subtarget->isTarget64BitILP32() ? X86::EAX : X86::RAX;
1697 // RAX/EAX now acts like a return value.
2051 // the sret argument into %rax/%eax (depending on ABI) for the return.
2986 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3006 case X86::EAX: case X86::EDX: case X86::ECX:
7659 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7690 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7741 // emit "addl x@ntpoff,%eax" (local exec)
7742 // or "addl x@indntpoff,%eax" (initial exec)
7743 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7832 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7844 // mov eax, .tls$:tlsvar
8345 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8347 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8348 MVT::i32, eax.getValue(2));
8349 SDValue Ops[] = { eax, edx };
10066 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
11144 // Pass 'nest' parameter in EAX.
11146 NestReg = X86::EAX;
11931 case MVT::i32: Reg = X86::EAX; size = 4; break;
12079 // the small struct {f32, f32} is returned in (eax, edx). For f64,
12293 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
12295 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
12296 eax.getValue(2));
12298 SDValue Ops[] = { eax, edx };
12314 Regs64bit ? X86::RAX : X86::EAX,
12340 Regs64bit ? X86::RAX : X86::EAX,
12740 // eax = -1
12743 // v = eax
12766 // EAX = -1
12767 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
12771 // EAX is live into the sinkMBB
12772 sinkMBB->addLiveIn(X86::EAX);
12775 .addReg(X86::EAX);
12913 // EAX = t4
12914 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
12915 // t3 = EAX
12959 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
12970 // t1 = OP MI.val, EAX
12971 // EAX = t4
12972 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12973 // t3 = EAX
13181 // EAX = t4L
13185 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13186 // t3L = EAX
13256 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13257 // t3L = EAX
13423 // Copy EDX:EAX back from HiReg:LoReg
13424 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
13439 // Copy EDX:EAX back to t3H:t3L
13440 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
13540 // Address into RAX/EAX, other two args into ECX, EDX.
13542 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14084 .addReg(X86::EAX, RegState::ImplicitDefine);
14092 .addReg(Is64Bit ? X86::RAX : X86::EAX);
14156 .addReg(X86::EAX, RegState::Implicit)
14158 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
14172 // or EAX and doing an indirect call. The return value will then
14200 TII->get(X86::MOV32rm), X86::EAX)
14207 addDirectMem(MIB, X86::EAX);
14208 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14211 TII->get(X86::MOV32rm), X86::EAX)
14218 addDirectMem(MIB, X86::EAX);
14219 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14342 // EAX = 0
15432 // movl $0, %eax
15433 // cmovgl %edi, %eax
15435 // xorl %eax, %eax
15437 // cmovsl %eax, %edi
17836 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
17837 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
17839 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
18282 // 'A' means EAX + EDX.
18284 Res.first = X86::EAX;
18292 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
18319 case X86::AX: DestReg = X86::EAX; break;
