Lines Matching full:pshuflw
3041 case X86ISD::PSHUFLW:
3081 case X86ISD::PSHUFLW:
3371 /// is suitable for input to PSHUFLW.
4134 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4647 case X86ISD::PSHUFLW:
5752 // 1. [all] pshuflw, pshufhw, optional move
5755 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5849 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5859 pshuflw = false;
5867 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5869 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5870 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5930 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5949 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
7002 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12522 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17628 case X86ISD::PSHUFLW:
