Lines Matching refs:ISD
76 if (Vec.getOpcode() == ISD::UNDEF)
89 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
90 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
94 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
109 if (Vec.getOpcode() == ISD::UNDEF)
127 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
237 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
248 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
249 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
250 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
251 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
252 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
253 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
257 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
259 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
267 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
270 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
275 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
276 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
290 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
295 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
296 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
300 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
306 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
308 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
309 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
314 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
315 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
316 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
319 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
320 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
327 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
331 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
337 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
342 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
343 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
345 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
347 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
363 setOperationAction(ISD::MULHS, VT, Expand);
364 setOperationAction(ISD::MULHU, VT, Expand);
365 setOperationAction(ISD::SDIV, VT, Expand);
366 setOperationAction(ISD::UDIV, VT, Expand);
367 setOperationAction(ISD::SREM, VT, Expand);
368 setOperationAction(ISD::UREM, VT, Expand);
371 setOperationAction(ISD::ADDC, VT, Custom);
372 setOperationAction(ISD::ADDE, VT, Custom);
373 setOperationAction(ISD::SUBC, VT, Custom);
374 setOperationAction(ISD::SUBE, VT, Custom);
377 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
378 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
379 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
380 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
381 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
382 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
383 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
384 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
385 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
386 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
388 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
389 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
390 setOperationAction(ISD
391 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
392 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
393 setOperationAction(ISD::FREM , MVT::f32 , Expand);
394 setOperationAction(ISD::FREM , MVT::f64 , Expand);
395 setOperationAction(ISD::FREM , MVT::f80 , Expand);
396 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
400 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
401 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
402 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
403 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
405 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
406 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
408 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
410 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
411 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
413 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
419 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
420 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
421 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
422 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
423 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
424 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
426 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
428 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
429 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
430 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
431 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
432 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
433 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
435 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
436 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
441 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
443 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
444 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
445 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
447 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
450 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
451 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
454 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
456 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
457 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
458 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
459 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
460 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
461 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
462 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
463 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
464 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
465 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
466 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
467 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
469 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
470 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
472 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
479 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
480 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
483 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
484 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
485 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
486 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
488 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
489 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
490 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
492 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
493 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
494 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
495 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
496 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
499 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
500 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
501 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
503 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
504 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
505 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
509 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
511 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
512 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
524 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
525 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
526 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
530 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
531 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
532 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
533 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
534 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
535 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
536 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
537 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
538 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
539 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
540 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
541 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
545 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
552 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
555 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
556 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
557 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
558 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
566 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
567 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
569 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
570 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
572 setOperationAction(ISD::TRAP, MVT::Other, Legal);
573 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
576 setOperationAction(ISD::VASTART , MVT::Other, Custom);
577 setOperationAction(ISD::VAEND , MVT::Other, Expand);
579 setOperationAction(ISD::VAARG , MVT::Other, Custom);
580 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
582 setOperationAction(ISD::VAARG , MVT::Other, Expand);
583 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
586 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
587 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
590 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
593 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
596 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
606 setOperationAction(ISD::FABS , MVT::f64, Custom);
607 setOperationAction(ISD::FABS , MVT::f32, Custom);
610 setOperationAction(ISD::FNEG , MVT::f64, Custom);
611 setOperationAction(ISD::FNEG , MVT::f32, Custom);
614 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
615 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
618 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
619 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
622 setOperationAction(ISD::FSIN , MVT::f64, Expand);
623 setOperationAction(ISD::FCOS , MVT::f64, Expand);
624 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
625 setOperationAction(ISD::FSIN , MVT::f32, Expand);
626 setOperationAction(ISD::FCOS , MVT::f32, Expand);
627 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
640 setOperationAction(ISD::FABS , MVT::f32, Custom);
643 setOperationAction(ISD::FNEG , MVT::f32, Custom);
645 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
648 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
649 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
652 setOperationAction(ISD::FSIN , MVT::f32, Expand);
653 setOperationAction(ISD::FCOS , MVT::f32, Expand);
654 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
664 setOperationAction(ISD::FSIN , MVT::f64, Expand);
665 setOperationAction(ISD::FCOS , MVT::f64, Expand);
666 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
674 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
675 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
676 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
677 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
680 setOperationAction(ISD::FSIN , MVT::f64, Expand);
681 setOperationAction(ISD::FSIN , MVT::f32, Expand);
682 setOperationAction(ISD::FCOS , MVT::f64, Expand);
683 setOperationAction(ISD::FCOS , MVT::f32, Expand);
684 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
685 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 setOperationAction(ISD::FMA, MVT::f64, Expand);
699 setOperationAction(ISD::FMA, MVT::f32, Expand);
704 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
705 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
722 setOperationAction(ISD::FSIN , MVT::f80, Expand);
723 setOperationAction(ISD::FCOS , MVT::f80, Expand);
724 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
727 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
728 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
729 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
730 setOperationAction(ISD::FRINT, MVT::f80, Expand);
731 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
732 setOperationAction(ISD::FMA, MVT::f80, Expand);
736 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
737 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
738 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
740 setOperationAction(ISD::FLOG, MVT::f80, Expand);
741 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
742 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
743 setOperationAction(ISD::FEXP, MVT::f80, Expand);
744 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
752 setOperationAction(ISD
753 setOperationAction(ISD::SUB , VT, Expand);
754 setOperationAction(ISD::FADD, VT, Expand);
755 setOperationAction(ISD::FNEG, VT, Expand);
756 setOperationAction(ISD::FSUB, VT, Expand);
757 setOperationAction(ISD::MUL , VT, Expand);
758 setOperationAction(ISD::FMUL, VT, Expand);
759 setOperationAction(ISD::SDIV, VT, Expand);
760 setOperationAction(ISD::UDIV, VT, Expand);
761 setOperationAction(ISD::FDIV, VT, Expand);
762 setOperationAction(ISD::SREM, VT, Expand);
763 setOperationAction(ISD::UREM, VT, Expand);
764 setOperationAction(ISD::LOAD, VT, Expand);
765 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
766 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
767 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
768 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
769 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
770 setOperationAction(ISD::FABS, VT, Expand);
771 setOperationAction(ISD::FSIN, VT, Expand);
772 setOperationAction(ISD::FSINCOS, VT, Expand);
773 setOperationAction(ISD::FCOS, VT, Expand);
774 setOperationAction(ISD::FSINCOS, VT, Expand);
775 setOperationAction(ISD::FREM, VT, Expand);
776 setOperationAction(ISD::FMA, VT, Expand);
777 setOperationAction(ISD::FPOWI, VT, Expand);
778 setOperationAction(ISD::FSQRT, VT, Expand);
779 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
780 setOperationAction(ISD::FFLOOR, VT, Expand);
781 setOperationAction(ISD::FCEIL, VT, Expand);
782 setOperationAction(ISD::FTRUNC, VT, Expand);
783 setOperationAction(ISD::FRINT, VT, Expand);
784 setOperationAction(ISD::FNEARBYINT, VT, Expand);
785 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
786 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
787 setOperationAction(ISD::SDIVREM, VT, Expand);
788 setOperationAction(ISD::UDIVREM, VT, Expand);
789 setOperationAction(ISD::FPOW, VT, Expand);
790 setOperationAction(ISD::CTPOP, VT, Expand);
791 setOperationAction(ISD::CTTZ, VT, Expand);
792 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
793 setOperationAction(ISD::CTLZ, VT, Expand);
794 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
795 setOperationAction(ISD::SHL, VT, Expand);
796 setOperationAction(ISD::SRA, VT, Expand);
797 setOperationAction(ISD::SRL, VT, Expand);
798 setOperationAction(ISD::ROTL, VT, Expand);
799 setOperationAction(ISD::ROTR, VT, Expand);
800 setOperationAction(ISD::BSWAP, VT, Expand);
801 setOperationAction(ISD::SETCC, VT, Expand);
802 setOperationAction(ISD::FLOG, VT, Expand);
803 setOperationAction(ISD::FLOG2, VT, Expand);
804 setOperationAction(ISD::FLOG10, VT, Expand);
805 setOperationAction(ISD::FEXP, VT, Expand);
806 setOperationAction(ISD::FEXP2, VT, Expand);
807 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
808 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
809 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
810 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
811 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
812 setOperationAction(ISD::TRUNCATE, VT, Expand);
813 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
814 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
815 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
816 setOperationAction(ISD::VSELECT, VT, Expand);
821 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
822 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
823 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
835 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
836 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
837 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
838 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
839 setOperationAction(ISD::AND, MVT::v8i8, Expand);
840 setOperationAction(ISD::AND, MVT::v4i16, Expand);
841 setOperationAction(ISD::AND, MVT::v2i32, Expand);
842 setOperationAction(ISD::AND, MVT::v1i64, Expand);
843 setOperationAction(ISD::OR, MVT::v8i8, Expand);
844 setOperationAction(ISD::OR, MVT::v4i16, Expand);
845 setOperationAction(ISD::OR, MVT::v2i32, Expand);
846 setOperationAction(ISD::OR, MVT::v1i64, Expand);
847 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
848 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
849 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
850 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
851 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
852 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
853 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
854 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
856 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
857 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
858 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
859 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
860 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
861 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
862 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
863 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
868 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
869 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
870 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
871 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
872 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
873 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
874 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
875 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
876 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
878 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
879 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
892 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
893 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
894 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
895 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
896 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
897 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
898 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
899 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
900 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
901 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
902 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
903 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
904 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
905 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
906 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
907 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
908 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
909 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
911 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
912 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
913 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
914 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
919 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
931 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
932 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
933 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
936 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
937 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
938 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
939 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
940 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
944 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
945 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
956 setOperationAction(ISD::AND, VT, Promote);
957 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
958 setOperationAction(ISD::OR, VT, Promote);
959 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
960 setOperationAction(ISD::XOR, VT, Promote);
961 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
962 setOperationAction(ISD::LOAD, VT, Promote);
963 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
964 setOperationAction(ISD::SELECT, VT, Promote);
965 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
971 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
972 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
973 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
974 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
976 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
977 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
979 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
980 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
984 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
986 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
987 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
989 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
993 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
994 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
995 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
996 setOperationAction(ISD::FRINT, MVT::f32, Legal);
997 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
998 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
999 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1000 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1001 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1002 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1004 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1005 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1006 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1007 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1008 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1009 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1010 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1011 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1012 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1013 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1016 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1018 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1019 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1020 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1021 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1022 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1028 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1029 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1030 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1031 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1033 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1034 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1035 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1041 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1042 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1048 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1050 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1051 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1053 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1054 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1057 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1058 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1060 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1061 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1063 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1065 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1066 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1068 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1069 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1071 ISD::SRA, MVT::v4i32, Custom);
1073 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1074 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1085 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1086 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1087 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1089 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1090 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1091 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1092 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1093 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1094 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1095 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1096 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1097 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1098 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1099 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1100 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1102 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1103 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1104 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1105 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1106 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1107 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1108 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1109 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1110 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1111 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1112 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1113 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1115 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1116 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1118 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1120 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1121 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1122 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1124 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1125 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1126 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1128 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1130 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1131 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1133 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1134 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1136 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1137 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1139 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1141 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1142 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1143 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1144 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1146 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1147 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1148 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1150 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1152 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1153 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1155 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1156 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1157 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1158 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1159 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1160 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1163 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1164 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1165 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1166 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1167 setOperationAction(ISD::FMA, MVT::f32, Legal);
1168 setOperationAction(ISD::FMA, MVT::f64, Legal);
1172 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1173 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1174 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1175 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1177 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1178 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1179 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1180 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1182 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1183 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1184 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1187 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1189 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1190 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1192 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1193 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1195 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1197 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1199 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1200 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1201 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1202 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1204 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1205 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1206 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1207 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1209 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1210 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1211 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1214 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1215 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1217 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1218 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1220 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1231 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1237 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1238 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1239 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1240 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1241 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1242 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1243 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1254 setOperationAction(ISD::AND, VT, Promote);
1255 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1256 setOperationAction(ISD::OR, VT, Promote);
1257 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1258 setOperationAction(ISD::XOR, VT, Promote);
1259 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1260 setOperationAction(ISD::LOAD, VT, Promote);
1261 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1262 setOperationAction(ISD::SELECT, VT, Promote);
1263 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1271 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1276 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1277 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1288 setOperationAction(ISD::SADDO, VT, Custom);
1289 setOperationAction(ISD::UADDO, VT, Custom);
1290 setOperationAction(ISD::SSUBO, VT, Custom);
1291 setOperationAction(ISD::USUBO, VT, Custom);
1292 setOperationAction(ISD::SMULO, VT, Custom);
1293 setOperationAction(ISD::UMULO, VT, Custom);
1297 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1298 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1315 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1316 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1321 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1322 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1323 setTargetDAGCombine(ISD::VSELECT);
1324 setTargetDAGCombine(ISD::SELECT);
1325 setTargetDAGCombine(ISD::SHL);
1326 setTargetDAGCombine(ISD::SRA);
1327 setTargetDAGCombine(ISD::SRL);
1328 setTargetDAGCombine(ISD::OR);
1329 setTargetDAGCombine(ISD::AND);
1330 setTargetDAGCombine(ISD::ADD);
1331 setTargetDAGCombine(ISD::FADD);
1332 setTargetDAGCombine(ISD::FSUB);
1333 setTargetDAGCombine(ISD::FMA);
1334 setTargetDAGCombine(ISD::SUB);
1335 setTargetDAGCombine(ISD::LOAD);
1336 setTargetDAGCombine(ISD::STORE);
1337 setTargetDAGCombine(ISD::ZERO_EXTEND);
1338 setTargetDAGCombine(ISD::ANY_EXTEND);
1339 setTargetDAGCombine(ISD::SIGN_EXTEND);
1340 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1341 setTargetDAGCombine(ISD::TRUNCATE);
1342 setTargetDAGCombine(ISD::SINT_TO_FP);
1343 setTargetDAGCombine(ISD::SETCC);
1345 setTargetDAGCombine(ISD::MUL);
1346 setTargetDAGCombine(ISD::XOR);
1586 const SmallVectorImpl<ISD::OutputArg> &Outs,
1597 const SmallVectorImpl<ISD::OutputArg> &Outs,
1624 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1626 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1628 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1630 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1653 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1664 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1665 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1670 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1719 if (Copy->getOpcode() == ISD::CopyToReg) {
1725 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1745 ISD::NodeType ExtendKind) const {
1748 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1763 const SmallVectorImpl<ISD::InputArg> &Ins,
1804 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1837 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1841 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1852 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1856 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1870 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1908 const SmallVectorImpl<ISD::InputArg> &Ins,
1914 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1950 const SmallVectorImpl<ISD::InputArg> &Ins,
2022 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2025 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2028 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2035 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2152 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2192 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2228 ISD::ArgFlagsTy Flags) const {
2231 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2280 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2282 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2373 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2381 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2384 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2389 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2390 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2393 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2396 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2436 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2506 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2520 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2536 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2571 unsigned WrapperKind = ISD::DELETED_NODE;
2606 if (WrapperKind != ISD::DELETED_NODE)
2768 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2773 if (Arg.getOpcode() == ISD::CopyFromReg) {
2805 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2828 const SmallVectorImpl<ISD::OutputArg> &Outs,
2830 const SmallVectorImpl<ISD::InputArg> &Ins,
2973 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3029 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3033 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3189 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3192 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3196 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3201 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3205 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3214 case ISD::SETEQ: return X86::COND_E;
3215 case ISD::SETGT: return X86::COND_G;
3216 case ISD::SETGE: return X86::COND_GE;
3217 case ISD::SETLT: return X86::COND_L;
3218 case ISD::SETLE: return X86::COND_LE;
3219 case ISD::SETNE: return X86::COND_NE;
3220 case ISD::SETULT: return X86::COND_B;
3221 case ISD::SETUGT: return X86::COND_A;
3222 case ISD::SETULE: return X86::COND_BE;
3223 case ISD::SETUGE: return X86::COND_AE;
3230 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3231 !ISD::isNON_EXTLoad(RHS.getNode())) {
3238 case ISD::SETOLT:
3239 case ISD::SETOLE:
3240 case ISD::SETUGT:
3241 case ISD::SETUGE:
3254 case ISD::SETUEQ:
3255 case ISD::SETEQ: return X86::COND_E;
3256 case ISD::SETOLT: // flipped
3257 case ISD::SETOGT:
3258 case ISD::SETGT: return X86::COND_A;
3259 case ISD::SETOLE: // flipped
3260 case ISD::SETOGE:
3261 case ISD::SETGE: return X86::COND_AE;
3262 case ISD::SETUGT: // flipped
3263 case ISD::SETULT:
3264 case ISD::SETLT: return X86::COND_B;
3265 case ISD::SETUGE: // flipped
3266 case ISD::SETULE:
3267 case ISD::SETLE: return X86::COND_BE;
3268 case ISD::SETONE:
3269 case ISD::SETNE: return X86::COND_NE;
3270 case ISD::SETUO: return X86::COND_P;
3271 case ISD::SETO: return X86::COND_NP;
3272 case ISD::SETOEQ:
3273 case ISD::SETUNE: return X86::COND_INVALID;
3651 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4290 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4293 if (!ISD::isNON_EXTLoad(N))
4303 if (N->getOpcode() != ISD::BUILD_VECTOR)
4309 case ISD::UNDEF:
4310 case ISD::ConstantFP:
4311 case ISD::Constant:
4319 return !ISD::isBuildVectorAllZeros(N) &&
4320 !ISD::isBuildVectorAllOnes(N);
4333 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4337 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4356 if (N->getOpcode() != ISD::BUILD_VECTOR)
4377 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4379 if (Opc != ISD::BUILD_VECTOR ||
4384 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4386 if (Opc != ISD::BUILD_VECTOR ||
4406 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4409 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4415 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4421 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4426 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4442 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4444 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4448 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4452 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4528 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4539 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4545 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4581 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4698 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4732 if (Opcode == ISD::BITCAST) {
4741 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4745 if (V.getOpcode() == ISD::BUILD_VECTOR)
4762 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4908 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4912 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4913 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4916 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4921 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4926 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4952 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4969 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4970 return DAG.getNode(ISD::BITCAST, dl, VT,
4985 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5030 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
5075 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5078 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5084 if (Elt.getOpcode() == ISD::UNDEF)
5122 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5129 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5160 case ISD::BUILD_VECTOR: {
5166 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5167 Ld.getOpcode() == ISD::ConstantFP);
5177 case ISD::VECTOR_SHUFFLE: {
5186 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5187 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5199 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5200 Ld.getOpcode() == ISD::ConstantFP);
5240 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5271 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5285 if (Opc == ISD::UNDEF)
5288 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5333 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5349 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5361 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5381 if (Elt.getOpcode() == ISD::UNDEF)
5384 if (Elt.getOpcode() != ISD::Constant &&
5385 Elt.getOpcode() != ISD::ConstantFP)
5419 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5420 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5433 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5443 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5449 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5453 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5459 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5460 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5468 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5478 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5492 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5533 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5534 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5546 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5574 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5624 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5625 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5630 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5631 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5641 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5642 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5659 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5742 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
5743 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
5748 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5831 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5832 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5833 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5905 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5907 DAG.getNode(ISD::BUILD_VECTOR, dl,
5910 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5922 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5924 DAG.getNode(ISD::BUILD_VECTOR, dl,
5926 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5927 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5947 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5971 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5997 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5999 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6001 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6046 DAG.getNode(ISD::BUILD_VECTOR, dl,
6051 if (V2.getOpcode() == ISD::UNDEF ||
6052 ISD::isBuildVectorAllZeros(V2.getNode()))
6064 DAG.getNode(ISD::BUILD_VECTOR, dl,
6066 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6072 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6073 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6094 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6096 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6105 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6108 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6112 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6120 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6123 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6127 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6129 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6132 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6135 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6149 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6150 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6151 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6179 DAG.getNode(ISD::BUILD_VECTOR, dl,
6221 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6222 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6240 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6241 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6245 return DAG.getNode(ISD::BITCAST, dl, VT,
6247 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6255 return DAG.getNode(ISD::BITCAST, dl, VT,
6257 DAG.getNode(ISD::BITCAST, dl,
6345 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6351 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6372 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6518 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6521 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6523 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6524 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6536 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6537 return DAG.getNode(ISD::BITCAST, dl, VT,
6555 return DAG.getNode(ISD::BITCAST, dl, VT,
6557 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6558 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6570 if (V2.getOpcode() == ISD::UNDEF)
6655 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
6690 if (V1.getOpcode() == ISD::BITCAST &&
6691 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6692 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6702 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
6712 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
6715 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
6719 return DAG.getNode(ISD::BITCAST, DL, VT,
6753 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6758 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6767 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6788 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6789 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6882 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7047 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
7051 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7105 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7107 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7114 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7115 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7116 DAG.getNode(ISD::BITCAST, dl,
7122 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7124 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7136 if ((User->getOpcode() != ISD::STORE ||
7139 (User->getOpcode() != ISD::BITCAST ||
7142 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7143 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7146 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7179 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7198 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7199 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7200 DAG.getNode(ISD::BITCAST, dl,
7207 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7209 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7222 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7241 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7273 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7290 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7324 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7341 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7362 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7370 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7372 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7374 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7375 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7450 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7483 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7522 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7557 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7591 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7605 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7648 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7662 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7706 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7709 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7751 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7763 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7814 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7819 // Lowering the machine isd will make sure everything is in the right
7876 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7885 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7887 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7899 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7912 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7916 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7921 if (Op.getOpcode() == ISD::SHL_PARTS) {
7923 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7926 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7929 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7939 if (Op.getOpcode() == ISD::SHL_PARTS) {
8080 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8086 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8092 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8093 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8100 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8103 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8104 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8108 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8121 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8127 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8128 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8132 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8133 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8134 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8136 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8137 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8139 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8140 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8144 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8150 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8153 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8171 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8172 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8187 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8202 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8239 ISD::SETLT);
8249 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8251 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8255 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8259 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8260 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8351 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8386 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8393 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8394 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8396 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8439 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8452 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8455 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8460 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8462 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8465 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8466 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8482 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8497 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8500 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8505 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8507 return DAG.getNode(ISD::BITCAST, DL, VT, In);
8510 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8513 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8516 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8517 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8527 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8528 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8533 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8553 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8555 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8564 return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), VT,
8565 DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(),
8612 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
8641 return DAG.getNode(ISD::BITCAST, dl, VT,
8642 DAG.getNode(ISD::AND, dl, ANDVT,
8643 DAG.getNode(ISD::BITCAST, dl, ANDVT,
8645 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
8675 return DAG.getNode(ISD::BITCAST, dl, VT,
8676 DAG.getNode(ISD::XOR, dl, XORVT,
8677 DAG.getNode(ISD::BITCAST, dl, XORVT,
8679 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8695 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8700 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8730 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8733 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8734 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8769 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8772 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8779 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
8802 if (I->getOpcode() == ISD::OR) {
8811 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8853 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
8861 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
8907 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8913 case ISD::ADD:
8914 case ISD::SUB:
8915 case ISD::AND:
8916 case ISD::OR:
8917 case ISD::XOR: {
8928 case ISD::ADD:
8941 if (UI->getOpcode() != ISD::CopyToReg &&
8942 UI->getOpcode() != ISD::SETCC &&
8943 UI->getOpcode() != ISD::STORE)
8967 case ISD::AND: {
8975 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8981 if (User->getOpcode() != ISD::BRCOND &&
8982 User->getOpcode() != ISD::SETCC &&
8983 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
8993 case ISD::SUB:
8994 case ISD::OR:
8995 case ISD::XOR:
9000 if (UI->getOpcode() == ISD::STORE)
9006 case ISD::SUB: Opcode = X86ISD::SUB; break;
9007 case ISD::XOR: Opcode = X86ISD::XOR; break;
9008 case ISD::AND: Opcode = X86ISD::AND; break;
9009 case ISD::OR: {
9047 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9048 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9049 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9050 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9051 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9057 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9058 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9115 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9117 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9119 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9130 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9134 if (Op0.getOpcode() == ISD::TRUNCATE)
9136 if (Op1.getOpcode() == ISD::TRUNCATE)
9140 if (Op1.getOpcode() == ISD::SHL)
9142 if (Op0.getOpcode() == ISD::SHL) {
9158 } else if (Op1.getOpcode() == ISD::Constant) {
9163 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9179 if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) {
9191 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9196 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9199 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9215 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9235 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9247 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9271 case ISD::SETOEQ:
9272 case ISD::SETEQ: SSECC = 0; break;
9273 case ISD::SETOGT:
9274 case ISD::SETGT: Swap = true; // Fallthrough
9275 case ISD::SETLT:
9276 case ISD::SETOLT: SSECC = 1; break;
9277 case ISD::SETOGE:
9278 case ISD::SETGE: Swap = true; // Fallthrough
9279 case ISD::SETLE:
9280 case ISD::SETOLE: SSECC = 2; break;
9281 case ISD::SETUO: SSECC = 3; break;
9282 case ISD::SETUNE:
9283 case ISD::SETNE: SSECC = 4; break;
9284 case ISD::SETULE: Swap = true; // Fallthrough
9285 case ISD::SETUGE: SSECC = 5; break;
9286 case ISD::SETULT: Swap = true; // Fallthrough
9287 case ISD::SETUGT: SSECC = 6; break;
9288 case ISD::SETO: SSECC = 7; break;
9289 case ISD::SETUEQ:
9290 case ISD::SETONE: SSECC = 8; break;
9299 if (SetCCOpcode == ISD::SETUEQ) {
9300 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9302 assert(SetCCOpcode == ISD::SETONE);
9303 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9329 case ISD::SETNE: Invert = true;
9330 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
9331 case ISD::SETLT: Swap = true;
9332 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
9333 case ISD::SETGE: Swap = true;
9334 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
9335 case ISD::SETULT: Swap = true;
9336 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
9337 case ISD::SETUGE: Swap = true;
9338 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
9354 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9355 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9363 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9368 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9379 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
9381 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
9382 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
9404 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9410 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9411 Op1.getOpcode() == ISD::Constant &&
9413 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9421 if (Op1.getOpcode() == ISD::Constant &&
9424 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9430 bool Invert = (CC == ISD::SETNE) ^
9483 if (V.getOpcode() != ISD::TRUNCATE)
9500 if (Cond.getOpcode() == ISD::SETCC) {
9551 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
9557 if (Cond.getOpcode() == ISD::AND &&
9585 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9586 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9587 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9595 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9596 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9597 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9598 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9599 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9600 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9603 if (CondOpcode == ISD::UMULO)
9611 if (CondOpcode == ISD::UMULO)
9627 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9628 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
9664 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
9668 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
9671 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
9726 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9729 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
9730 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
9734 if (Opc != ISD::OR && Opc != ISD::AND)
9742 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
9745 if (Op.getOpcode() != ISD::XOR)
9764 if (Cond.getOpcode() == ISD::SETCC) {
9766 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9770 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9771 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9772 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9773 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9774 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9775 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9794 if (Cond.getOpcode() == ISD::AND &&
9828 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9829 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9830 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9838 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9839 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9840 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9841 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9842 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9843 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9848 if (CondOpcode == ISD::UMULO)
9856 if (CondOpcode == ISD::UMULO)
9867 if (CondOpc == ISD::OR) {
9880 } else { // ISD::AND
9897 if (User->getOpcode() == ISD::BR) {
9926 } else if (Cond.getOpcode() == ISD::SETCC &&
9927 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9938 if (User->getOpcode() == ISD::BR) {
9957 } else if (Cond.getOpcode() == ISD::SETCC &&
9958 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9969 if (User->getOpcode() == ISD::BR) {
9998 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9999 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10114 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10123 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10133 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10140 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10263 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10270 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10305 ISD::CondCode CC;
10311 CC = ISD::SETEQ;
10316 CC = ISD::SETLT;
10321 CC = ISD::SETLE;
10326 CC = ISD::SETGT;
10331 CC = ISD::SETGE;
10336 CC = ISD::SETNE;
10341 CC = ISD::SETEQ;
10346 CC = ISD::SETLT;
10351 CC = ISD::SETLE;
10356 CC = ISD::SETGT;
10361 CC = ISD::SETGE;
10366 CC = ISD::SETNE;
10377 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10555 Opcode = ISD::SHL;
10561 Opcode = ISD::SRL;
10565 Opcode = ISD::SRA;
10608 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
10673 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10832 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10944 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10964 DAG.getNode(ISD::ADD, dl, PtrVT,
11007 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
11009 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
11068 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11077 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11083 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11091 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11098 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11104 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11153 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11155 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11165 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11172 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11178 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11184 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11235 DAG.getNode(ISD::SRL, DL, MVT::i16,
11236 DAG.getNode(ISD::AND, DL, MVT::i16,
11240 DAG.getNode(ISD::SRL, DL, MVT::i16,
11241 DAG.getNode(ISD::AND, DL, MVT::i16,
11246 DAG.getNode(ISD::AND, DL, MVT::i16,
11247 DAG.getNode(ISD::ADD, DL, MVT::i16,
11248 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11253 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
11266 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11283 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11286 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11300 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11308 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11311 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11359 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
11405 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
11406 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
11435 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
11436 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
11437 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
11438 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
11447 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
11448 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
11478 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
11488 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
11489 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
11513 if (Op.getOpcode() == ISD::SHL)
11516 if (Op.getOpcode() == ISD::SRL)
11519 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11525 if (Op.getOpcode() == ISD::SHL) {
11529 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11534 return DAG.getNode(ISD::AND, dl, VT, SHL,
11535 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11537 if (Op.getOpcode() == ISD::SRL) {
11541 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11546 return DAG.getNode(ISD::AND, dl, VT, SRL,
11547 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11549 if (Op.getOpcode() == ISD::SRA) {
11557 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11560 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
11561 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11562 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11569 if (Op.getOpcode() == ISD::SHL) {
11573 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11578 return DAG.getNode(ISD::AND, dl, VT, SHL,
11579 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11581 if (Op.getOpcode() == ISD::SRL) {
11585 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11590 return DAG.getNode(ISD::AND, dl, VT, SRL,
11591 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11593 if (Op.getOpcode() == ISD::SRA) {
11601 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11604 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
11605 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11606 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11615 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
11616 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
11618 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
11619 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
11620 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
11621 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
11623 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11627 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
11628 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
11632 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11639 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
11642 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11643 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11646 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11647 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11651 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
11654 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11655 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11658 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11659 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11663 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
11664 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
11680 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11689 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11691 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11704 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
11723 case ISD::SADDO:
11735 case ISD::UADDO:
11739 ISD::SSUBO:
11751 case ISD::USUBO:
11755 case ISD::SMULO:
11759 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
11769 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11782 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11825 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
11963 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
11966 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
11996 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
11998 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
12020 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
12046 case ISD::ADDC: Opc = X86ISD::ADD; break;
12047 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
12048 case ISD::SUBC: Opc = X86ISD::SUB; break;
12049 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
12101 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
12102 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG);
12103 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
12104 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
12105 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
12106 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
12107 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
12108 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
12109 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
12110 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
12111 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
12112 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
12113 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
12114 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
12115 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
12116 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
12117 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
12118 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
12119 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
12120 case ISD::SHL_PARTS:
12121 case ISD::SRA_PARTS:
12122 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
12123 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
12124 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
12125 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
12126 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
12127 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
12128 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, DAG);
12129 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
12130 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
12131 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
12132 case ISD
12133 case ISD::FNEG: return LowerFNEG(Op, DAG);
12134 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
12135 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
12136 case ISD::SETCC: return LowerSETCC(Op, DAG);
12137 case ISD::SELECT: return LowerSELECT(Op, DAG);
12138 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
12139 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
12140 case ISD::VASTART: return LowerVASTART(Op, DAG);
12141 case ISD::VAARG: return LowerVAARG(Op, DAG);
12142 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
12143 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
12144 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
12145 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
12146 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
12147 case ISD::FRAME_TO_ARGS_OFFSET:
12149 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
12150 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
12151 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
12152 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
12153 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
12154 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
12155 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
12156 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
12157 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
12158 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
12159 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
12160 case ISD::SRA:
12161 case ISD::SRL:
12162 case ISD::SHL: return LowerShift(Op, DAG);
12163 case ISD::SADDO:
12164 case ISD::UADDO:
12165 case ISD::SSUBO:
12166 case ISD::USUBO:
12167 case ISD::SMULO:
12168 case ISD::UMULO: return LowerXALUO(Op, DAG);
12169 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
12170 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
12171 case ISD::ADDC:
12172 case ISD::ADDE:
12173 case ISD::SUBC:
12174 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
12175 case ISD::ADD: return LowerADD(Op, DAG);
12176 case ISD::SUB: return LowerSUB(Op, DAG);
12177 case ISD::SDIV: return LowerSDIV(Op, DAG);
12178 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
12193 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
12212 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12214 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12222 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
12236 case ISD::SIGN_EXTEND_INREG:
12237 case ISD::ADDC:
12238 case ISD::ADDE:
12239 case ISD::SUBC:
12240 case ISD::SUBE:
12243 case ISD::FP_TO_SINT:
12244 case ISD::FP_TO_UINT: {
12245 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
12265 case ISD::UINT_TO_FP: {
12270 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
12274 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
12275 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
12276 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
12277 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
12278 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
12282 case ISD::FP_ROUND: {
12289 case ISD::READCYCLECOUNTER: {
12299 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
12303 case ISD::ATOMIC_CMP_SWAP: {
12309 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12311 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12320 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12322 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12346 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
12350 case ISD::ATOMIC_LOAD_ADD:
12351 case ISD::ATOMIC_LOAD_AND:
12352 case ISD::ATOMIC_LOAD_NAND:
12353 case ISD::ATOMIC_LOAD_OR:
12354 case ISD::ATOMIC_LOAD_SUB:
12355 case ISD::ATOMIC_LOAD_XOR:
12356 case ISD::ATOMIC_LOAD_MAX:
12357 case ISD::ATOMIC_LOAD_MIN:
12358 case ISD::ATOMIC_LOAD_UMAX:
12359 case ISD::ATOMIC_LOAD_UMIN:
12360 case ISD::ATOMIC_SWAP: {
12364 case ISD::ATOMIC_LOAD_ADD:
12367 case ISD::ATOMIC_LOAD_AND:
12370 case ISD::ATOMIC_LOAD_NAND:
12373 case ISD::ATOMIC_LOAD_OR:
12376 case ISD::ATOMIC_LOAD_SUB:
12379 case ISD::ATOMIC_LOAD_XOR:
12382 case ISD::ATOMIC_LOAD_MAX:
12385 case ISD::ATOMIC_LOAD_MIN:
12388 case ISD::ATOMIC_LOAD_UMAX:
12391 case ISD::ATOMIC_LOAD_UMIN:
12394 case ISD::ATOMIC_SWAP:
12401 case ISD::ATOMIC_LOAD:
12655 if (Val.getOpcode() != ISD::LOAD)
14661 assert((Opc >= ISD::BUILTIN_OP_END ||
14662 Opc == ISD::INTRINSIC_WO_CHAIN ||
14663 Opc == ISD::INTRINSIC_W_CHAIN ||
14664 Opc == ISD::INTRINSIC_VOID) &&
14689 case ISD::INTRINSIC_WO_CHAIN: {
14789 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
14790 V2.getOpcode() == ISD::CONCAT_VECTORS) {
14801 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
14802 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
14803 V1.getOperand(1).getOpcode() != ISD::UNDEF)
14806 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
14834 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
14841 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
14887 N->getOpcode() == ISD::VECTOR_SHUFFLE)
14931 if (InVec.getOpcode() == ISD::BITCAST) {
14965 if (LdNode.getOpcode() == ISD::BITCAST) {
14974 if (!ISD::isNormalLoad(LdNode.getNode()))
14990 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
15003 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
15004 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
15020 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
15043 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
15050 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
15051 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
15088 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
15131 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15138 case ISD::SETULT:
15139 case ISD::SETULE:
15141 case ISD::SETUGT:
15142 case ISD::SETUGE:
15144 case ISD::SETLT:
15145 case ISD::SETLE:
15147 case ISD::SETGT:
15148 case ISD::SETGE:
15156 case ISD::SETULT:
15157 case ISD::SETULE:
15159 case ISD::SETUGT:
15160 case ISD::SETUGE:
15162 case ISD::SETLT:
15163 case ISD::SETLE:
15165 case ISD::SETGT:
15166 case ISD::SETGE:
15190 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
15194 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15202 case ISD::SETULT:
15214 case ISD::SETOLE:
15222 case ISD::SETULE:
15226 case ISD::SETOLT:
15227 case ISD::SETLT:
15228 case ISD::SETLE:
15232 case ISD::SETOGE:
15240 case ISD::SETUGT:
15252 case ISD::SETUGE:
15256 case ISD::SETOGT:
15257 case ISD::SETGT:
15258 case ISD::SETGE:
15267 case ISD::SETOGE:
15279 case ISD::SETUGT:
15286 case ISD::SETUGE:
15290 case ISD::SETOGT:
15291 case ISD::SETGT:
15292 case ISD::SETGE:
15296 case ISD::SETULT:
15302 case ISD::SETOLE:
15314 case ISD::SETULE:
15318 case ISD::SETOLT:
15319 case ISD::SETLT:
15320 case ISD::SETLE:
15342 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
15343 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
15353 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15357 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
15360 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
15367 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15371 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15373 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15402 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15406 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15410 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15415 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15438 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
15441 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15444 case ISD::SETLT:
15445 case ISD::SETGT: {
15446 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
15449 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
15456 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
15460 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15465 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
15467 CC = ISD::getSetCCInverse(CC, true);
15468 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
15480 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
15481 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
15486 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
15499 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
15500 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
15511 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
15520 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
15521 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
15590 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
15697 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
15700 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
15714 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15716 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15751 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15755 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15760 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15848 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
15856 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
15863 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
15884 N1C && N0.getOpcode() == ISD::AND &&
15885 N0.getOperand(1).getOpcode() == ISD::Constant) {
15888 ((N00.getOpcode() == ISD::ANY_EXTEND ||
15889 N00.getOpcode() == ISD::ZERO_EXTEND) &&
15895 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
15911 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
15924 if (N->getOpcode() == ISD::SHL) {
15945 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
15950 if (Arg.getOpcode() == ISD::UNDEF) continue;
15961 if (Arg.getOpcode() == ISD::UNDEF) continue;
15966 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
15969 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15974 if (Arg.getOpcode() == ISD::UNDEF) continue;
15978 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15992 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
16000 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
16002 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
16009 case ISD::SHL:
16020 case ISD::SRA:
16029 case ISD::SRL:
16075 case ISD::BR_CC:
16076 case ISD::BRCOND:
16077 case ISD::SELECT:
16080 case ISD::CopyToReg:
16081 case ISD::SIGN_EXTEND:
16082 case ISD::ZERO_EXTEND:
16083 case ISD::ANY_EXTEND:
16107 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
16109 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
16111 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
16126 if (ISD::isBuildVectorAllOnes(N))
16130 if (N->getOpcode() == ISD::BITCAST)
16136 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
16140 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
16141 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
16142 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
16143 ISD::isBuildVectorAllOnes(V2.getNode()))
16161 assert((N->getOpcode() == ISD::ANY_EXTEND ||
16162 N->getOpcode() == ISD::ZERO_EXTEND ||
16163 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
16170 if (Narrow->getOpcode() != ISD::XOR &&
16171 Narrow->getOpcode() != ISD::AND &&
16172 Narrow->getOpcode() != ISD::OR)
16180 if (N0.getOpcode() != ISD::TRUNCATE)
16189 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
16203 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
16206 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
16215 case ISD::ANY_EXTEND:
16217 case ISD::ZERO_EXTEND: {
16221 return DAG.getNode(ISD::AND, DL, VT,
16224 case ISD::SIGN_EXTEND:
16225 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
16252 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
16257 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
16262 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16267 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16286 if (N0.getOpcode() == ISD::XOR &&
16287 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
16292 if (N1.getOpcode() == ISD::XOR &&
16293 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
16324 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
16339 if (Mask.getOpcode() == ISD::BITCAST)
16341 if (X.getOpcode() == ISD::BITCAST)
16343 if (Y.getOpcode() == ISD::BITCAST)
16366 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
16367 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
16372 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16380 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
16381 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
16382 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
16383 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
16384 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16392 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
16394 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
16405 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
16407 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
16414 if (ShAmt0.getOpcode() == ISD::SUB) {
16421 if (ShAmt1.getOpcode() == ISD::SUB) {
16425 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
16430 DAG.getNode(ISD::TRUNCATE, DL,
16439 DAG.getNode(ISD::TRUNCATE, DL,
16461 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
16462 N0.getOpcode() == ISD::ADD &&
16464 N1.getOpcode() == ISD::SRA &&
16509 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16513 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16531 ISD::LoadExtType Ext = Ld->getExtensionType();
16537 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
16551 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16556 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16574 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
16582 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
16608 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
16612 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16649 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16651 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16654 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16657 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16662 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16665 if (Ext == ISD::SEXTLOAD) {
16675 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
16687 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16692 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
16708 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16744 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
16753 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
16782 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
16815 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
16823 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
16829 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16833 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16867 ChainVal->getOpcode() == ISD::TokenFactor) {
16877 if (!Ld || !ISD::isNormalLoad(Ld))
16900 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16911 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
16928 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16933 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
16945 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
16976 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
16977 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
17002 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17003 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
17005 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
17010 if (LHS.getOpcode() != ISD::UNDEF)
17020 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17021 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
17023 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
17028 if (RHS.getOpcode() != ISD::UNDEF)
17176 if (Op.getOpcode() == ISD::BITCAST)
17182 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
17203 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
17204 N0.getOpcode() == ISD::SIGN_EXTEND)) {
17209 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
17210 if (!ISD::isNormalLoad(N00.getNode()))
17214 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
17216 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
17259 bool NegA = (A.getOpcode() == ISD::FNEG);
17260 ISD::FNEG);
17261 bool NegC = (C.getOpcode() == ISD::FNEG);
17287 // ISD::SETCC is always legalized to i8.
17292 if (N0.getOpcode() == ISD::AND &&
17300 return DAG.getNode(ISD::AND, dl, VT,
17319 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
17323 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
17326 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17331 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
17334 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17346 return DAG.getNode(ISD::AND, DL, MVT::i8,
17427 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
17428 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
17433 if (Op0.getOpcode() == ISD::LOAD) {
17437 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
17463 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
17482 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
17483 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
17504 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
17506 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
17509 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
17541 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
17545 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
17548 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
17569 while (In.getOpcode() == ISD::BITCAST)
17584 case ISD::EXTRACT_VECTOR_ELT:
17586 case ISD::VSELECT:
17587 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
17589 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
17590 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
17592 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
17593 case ISD::SHL:
17594 case ISD::SRA:
17595 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
17596 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
17597 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
17598 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
17599 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
17600 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
17601 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
17602 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
17603 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
17611 case ISD::ANY_EXTEND:
17612 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
17613 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
17614 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
17615 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
17616 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
17633 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
17634 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
17653 case ISD::LOAD:
17654 case ISD::SIGN_EXTEND:
17655 case ISD::ZERO_EXTEND:
17656 case ISD::ANY_EXTEND:
17657 case ISD::SHL:
17658 case ISD::SRL:
17659 case ISD::SUB:
17660 case ISD::ADD:
17661 case ISD::MUL:
17662 case ISD::AND:
17663 case ISD::OR:
17664 case ISD::XOR:
17681 case ISD::LOAD: {
17685 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
17691 if (UI->getOpcode() != ISD::CopyToReg)
17698 case ISD::SIGN_EXTEND:
17699 case ISD::ZERO_EXTEND:
17700 case ISD::ANY_EXTEND:
17703 case ISD::SHL:
17704 case ISD::SRL: {
17712 case ISD::ADD:
17713 case ISD::MUL:
17714 case ISD::AND:
17715 case ISD::OR:
17716 case ISD::XOR:
17719 case ISD::SUB: {
18110 } else if (Op.getOpcode() == ISD::ADD) {
18116 } else if (Op.getOpcode() == ISD::SUB) {
