Lines Matching refs:TII
2770 const X86InstrInfo *TII) {
2781 if (!TII->isLoadFromStackSlot(Def, FI))
2968 const X86InstrInfo *TII =
2978 MFI, MRI, TII))
12727 const TargetInstrInfo *TII) {
12761 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
12767 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
12774 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12923 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12992 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
13017 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
13037 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
13048 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
13050 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
13072 BuildMI(mainMBB, DL, TII->get(CMPOpc))
13079 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
13092 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
13094 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
13098 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
13103 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
13107 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
13117 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
13123 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
13132 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
13135 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13146 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
13149 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13156 TII->get(TargetOpcode::COPY), DstReg)
13196 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13279 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
13300 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
13319 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
13321 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
13335 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
13337 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
13346 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
13348 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
13350 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
13351 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
13366 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13368 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
13369 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
13371 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13373 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
13374 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
13377 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
13380 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
13385 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
13387 BuildMI(mainMBB, DL, TII
13389 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
13392 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
13399 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
13405 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
13407 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
13417 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
13418 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
13424 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
13425 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
13427 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
13428 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
13430 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13440 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
13441 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
13443 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13450 TII->get(TargetOpcode::COPY), DstLoReg)
13453 TII->get(TargetOpcode::COPY), DstHiReg)
13464 const TargetInstrInfo *TII) {
13479 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13491 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13501 const TargetInstrInfo *TII) {
13516 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13528 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13536 const TargetInstrInfo *TII,
13543 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
13548 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
13550 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
13554 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
13593 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13684 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
13693 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
13699 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
13709 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
13719 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
13725 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
13731 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
13736 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
13746 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
13756 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
13772 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
13776 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
13780 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
13787 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
13792 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
13804 TII->get(X86::PHI), DestReg)
13851 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13860 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
13861 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
13874 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
13928 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13974 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
13985 TII->get(X86::PHI), MI->getOperand(0).getReg())
13996 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14050 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
14051 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
14053 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
14056 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
14060 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
14062 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
14064 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14070 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
14072 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
14078 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
14080 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
14081 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
14088 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
14091 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
14093 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14102 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
14117 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14130 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
14141 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
14146 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
14154 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
14174 const X86InstrInfo *TII
14189 TII->get(X86::MOV64rm), X86::RDI)
14195 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
14200 TII->get(X86::MOV32rm), X86::EAX)
14206 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14211 TII->get(X86::MOV32rm), X86::EAX)
14212 .addReg(TII->getGlobalBaseReg(F))
14217 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14230 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14304 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
14311 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
14312 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
14322 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
14335 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
14343 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
14348 TII->get(X86::PHI), DstReg)
14353 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
14354 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
14365 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14394 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
14399 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
14408 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
14417 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
14470 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14478 TII->get(X86::FNSTCW16m)), CWFrameIdx);
14483 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
14487 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
14492 TII->get(X86::FLDCW16m)), CWFrameIdx);
14495 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
14534 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
14539 TII->get(X86::FLDCW16m)), CWFrameIdx);
