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1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
15 #include "X86.h"
49                            " fuse, but the X86 backend currently can't"),
95                      ? X86::ADJCALLSTACKDOWN64
96                      : X86::ADJCALLSTACKDOWN32),
98                      ? X86::ADJCALLSTACKUP64
99                      : X86::ADJCALLSTACKUP32)),
103     { X86::ADC32ri,     X86::ADC32mi,    0 },
104     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
105     { X86::ADC32rr,     X86::ADC32mr,    0 },
106     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
107     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
108     { X86::ADC64rr,     X86::ADC64mr,    0 },
109     { X86::ADD16ri,     X86::ADD16mi,    0 },
110     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
111     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
112     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
113     { X86::ADD16rr,     X86::ADD16mr,    0 },
114     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
115     { X86::ADD32ri,     X86::ADD32mi,    0 },
116     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
117     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
118     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
119     { X86::ADD32rr,     X86::ADD32mr,    0 },
120     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
121     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
122     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
123     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
124     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
125     { X86::ADD64rr,     X86::ADD64mr,    0 },
126     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
127     { X86::ADD8ri,      X86::ADD8mi,     0 },
128     { X86::ADD8rr,      X86::ADD8mr,     0 },
129     { X86::AND16ri,     X86::AND16mi,    0 },
130     { X86::AND16ri8,    X86::AND16mi8,   0 },
131     { X86::AND16rr,     X86::AND16mr,    0 },
132     { X86::AND32ri,     X86::AND32mi,    0 },
133     { X86::AND32ri8,    X86::AND32mi8,   0 },
134     { X86::AND32rr,     X86::AND32mr,    0 },
135     { X86::AND64ri32,   X86::AND64mi32,  0 },
136     { X86::AND64ri8,    X86::AND64mi8,   0 },
137     { X86::AND64rr,     X86::AND64mr,    0 },
138     { X86::AND8ri,      X86::AND8mi,     0 },
139     { X86::AND8rr,      X86::AND8mr,     0 },
140     { X86::DEC16r,      X86::DEC16m,     0 },
141     { X86::DEC32r,      X86::DEC32m,     0 },
142     { X86::DEC64_16r,   X86::DEC64_16m,  0 },
143     { X86::DEC64_32r,   X86::DEC64_32m,  0 },
144     { X86::DEC64r,      X86::DEC64m,     0 },
145     { X86::DEC8r,       X86::DEC8m,      0 },
146     { X86::INC16r,      X86::INC16m,     0 },
147     { X86::INC32r,      X86::INC32m,     0 },
148     { X86::INC64_16r,   X86::INC64_16m,  0 },
149     { X86::INC64_32r,   X86::INC64_32m,  0 },
150     { X86::INC64r,      X86::INC64m,     0 },
151     { X86::INC8r,       X86::INC8m,      0 },
152     { X86::NEG16r,      X86::NEG16m,     0 },
153     { X86::NEG32r,      X86::NEG32m,     0 },
154     { X86::NEG64r,      X86::NEG64m,     0 },
155     { X86::NEG8r,       X86::NEG8m,      0 },
156     { X86::NOT16r,      X86::NOT16m,     0 },
157     { X86::NOT32r,      X86::NOT32m,     0 },
158     { X86::NOT64r,      X86::NOT64m,     0 },
159     { X86::NOT8r,       X86::NOT8m,      0 },
160     { X86::OR16ri,      X86::OR16mi,     0 },
161     { X86::OR16ri8,     X86::OR16mi8,    0 },
162     { X86::OR16rr,      X86::OR16mr,     0 },
163     { X86::OR32ri,      X86::OR32mi,     0 },
164     { X86::OR32ri8,     X86::OR32mi8,    0 },
165     { X86::OR32rr,      X86::OR32mr,     0 },
166     { X86::OR64ri32,    X86::OR64mi32,   0 },
167     { X86::OR64ri8,     X86::OR64mi8,    0 },
168     { X86::OR64rr,      X86::OR64mr,     0 },
169     { X86::OR8ri,       X86::OR8mi,      0 },
170     { X86::OR8rr,       X86::OR8mr,      0 },
171     { X86::ROL16r1,     X86::ROL16m1,    0 },
172     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
173     { X86::ROL16ri,     X86::ROL16mi,    0 },
174     { X86::ROL32r1,     X86::ROL32m1,    0 },
175     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
176     { X86::ROL32ri,     X86::ROL32mi,    0 },
177     { X86::ROL64r1,     X86::ROL64m1,    0 },
178     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
179     { X86::ROL64ri,     X86::ROL64mi,    0 },
180     { X86::ROL8r1,      X86::ROL8m1,     0 },
181     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
182     { X86::ROL8ri,      X86::ROL8mi,     0 },
183     { X86::ROR16r1,     X86::ROR16m1,    0 },
184     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
185     { X86::ROR16ri,     X86::ROR16mi,    0 },
186     { X86::ROR32r1,     X86::ROR32m1,    0 },
187     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
188     { X86::ROR32ri,     X86::ROR32mi,    0 },
189     { X86::ROR64r1,     X86::ROR64m1,    0 },
190     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
191     { X86::ROR64ri,     X86::ROR64mi,    0 },
192     { X86::ROR8r1,      X86::ROR8m1,     0 },
193     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
194     { X86::ROR8ri,      X86::ROR8mi,     0 },
195     { X86::SAR16r1,     X86::SAR16m1,    0 },
196     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
197     { X86::SAR16ri,     X86::SAR16mi,    0 },
198     { X86::SAR32r1,     X86::SAR32m1,    0 },
199     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
200     { X86::SAR32ri,     X86::SAR32mi,    0 },
201     { X86::SAR64r1,     X86::SAR64m1,    0 },
202     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
203     { X86::SAR64ri,     X86::SAR64mi,    0 },
204     { X86::SAR8r1,      X86::SAR8m1,     0 },
205     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
206     { X86::SAR8ri,      X86::SAR8mi,     0 },
207     { X86::SBB32ri,     X86::SBB32mi,    0 },
208     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
209     { X86::SBB32rr,     X86::SBB32mr,    0 },
210     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
211     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
212     { X86::SBB64rr,     X86::SBB64mr,    0 },
213     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
214     { X86::SHL16ri,     X86::SHL16mi,    0 },
215     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
216     { X86::SHL32ri,     X86::SHL32mi,    0 },
217     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
218     { X86::SHL64ri,     X86::SHL64mi,    0 },
219     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
220     { X86::SHL8ri,      X86::SHL8mi,     0 },
221     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
222     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
223     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
224     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
225     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
226     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
227     { X86::SHR16r1,     X86::SHR16m1,    0 },
228     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
229     { X86::SHR16ri,     X86::SHR16mi,    0 },
230     { X86::SHR32r1,     X86::SHR32m1,    0 },
231     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
232     { X86::SHR32ri,     X86::SHR32mi,    0 },
233     { X86::SHR64r1,     X86::SHR64m1,    0 },
234     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
235     { X86::SHR64ri,     X86::SHR64mi,    0 },
236     { X86::SHR8r1,      X86::SHR8m1,     0 },
237     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
238     { X86::SHR8ri,      X86::SHR8mi,     0 },
239     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
240     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
241     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
242     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
243     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
244     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
245     { X86::SUB16ri,     X86::SUB16mi,    0 },
246     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
247     { X86::SUB16rr,     X86::SUB16mr,    0 },
248     { X86::SUB32ri,     X86::SUB32mi,    0 },
249     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
250     { X86::SUB32rr,     X86::SUB32mr,    0 },
251     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
252     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
253     { X86::SUB64rr,     X86::SUB64mr,    0 },
254     { X86::SUB8ri,      X86::SUB8mi,     0 },
255     { X86::SUB8rr,      X86::SUB8mr,     0 },
256     { X86::XOR16ri,     X86::XOR16mi,    0 },
257     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
258     { X86::XOR16rr,     X86::XOR16mr,    0 },
259     { X86::XOR32ri,     X86::XOR32mi,    0 },
260     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
261     { X86::XOR32rr,     X86::XOR32mr,    0 },
262     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
263     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
264     { X86::XOR64rr,     X86::XOR64mr,    0 },
265     { X86::XOR8ri,      X86::XOR8mi,     0 },
266     { X86::XOR8rr,      X86::XOR8mr,     0 }
280     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
281     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
282     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
283     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
284     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
285     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
286     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
287     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
288     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
289     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
290     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
291     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
292     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
293     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
294     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
295     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
296     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
297     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
298     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
299     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
300     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
301     { X86::FsMOVAPDrr,  X86::MOVSDmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
302     { X86::FsMOVAPSrr,  X86::MOVSSmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
303     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
304     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
305     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
306     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
307     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
308     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
309     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
310     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
311     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
312     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
313     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
314     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
315     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
316     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
317     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
318     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
319     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
320     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
321     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
322     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
323     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
326     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
327     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
328     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
329     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
330     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
331     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
332     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
333     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
334     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
335     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
336     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
337     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
338     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
339     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
340     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
341     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
342     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
343     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
344     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
345     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
346     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
347     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
348     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
349     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
350     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
351     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
352     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
353     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
354     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
355     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
356     { X86::TEST8ri,     X86
358     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
359     { X86::FsVMOVAPDrr, X86::VMOVSDmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
360     { X86::FsVMOVAPSrr, X86::VMOVSSmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
361     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
362     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
363     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
364     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
365     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
366     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
367     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
368     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
369     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
370     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
372     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
373     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
374     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
375     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
376     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
377     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE }
389     { X86::CMP16rr,         X86::CMP16rm,             0 },
390     { X86::CMP32rr,         X86::CMP32rm,             0 },
391     { X86::CMP64rr,         X86::CMP64rm,             0 },
392     { X86::CMP8rr,          X86::CMP8rm,              0 },
393     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
394     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
395     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
396     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
397     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
398     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
399     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
400     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
401     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
402     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
403     { X86::FsMOVAPDrr,      X86::MOVSDrm,             TB_NO_REVERSE },
404     { X86::FsMOVAPSrr,      X86::MOVSSrm,             TB_NO_REVERSE },
405     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
406     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
407     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
408     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
409     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
410     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
411     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
412     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
413     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
414     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
415     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
416     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
417     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
418     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
419     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
420     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
421     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
422     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
423     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
424     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
425     { X86::MOV16rr,         X86::MOV16rm,             0 },
426     { X86::MOV32rr,         X86::MOV32rm,             0 },
427     { X86::MOV64rr,         X86::MOV64rm,             0 },
428     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
429     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
430     { X86::MOV8rr,          X86::MOV8rm,              0 },
431     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
432     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
433     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
434     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
435     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
436     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
437     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
438     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
439     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
440     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
441     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
442     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
443     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
444     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
445     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
446     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
447     { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm,        0 },
448     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
449     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
450     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
451     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
452     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
453     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
454     { X86::MOVZX64rr16,     X86::MOVZX64rm16,         0 },
455     { X86::MOVZX64rr32,     X86::MOVZX64rm32,         0 },
456     { X86::MOVZX64rr8,      X86::MOVZX64rm8,          0 },
457     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
458     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
459     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
460     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
461     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
462     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
463     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
464     { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
465     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
466     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
467     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
468     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
469     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
470     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
471     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
472     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
473     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
474     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
475     { X86::TEST16rr,        X86::TEST16rm,            0 },
476     { X86::TEST32rr,        X86::TEST32rm,            0 },
477     { X86::TEST64rr,        X86::TEST64rm,            0 },
478     { X86::TEST8rr,         X86::TEST8rm,             0 },
480     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
481     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
483     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
484     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
485     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
486     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
487     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
488     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
489     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
490     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
491     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
492     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
493     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
494     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
495     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
496     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
497     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
498     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
499     { X86::FsVMOVAPDrr,     X86::VMOVSDrm,            TB_NO_REVERSE },
500     { X86::FsVMOVAPSrr,     X86::VMOVSSrm,            TB_NO_REVERSE },
501     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
502     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
503     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
504     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
505     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
506     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
507     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
508     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
509     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
510     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
511     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
512     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
513     { X86::VMOVZDI2PDIrr,   X86::VMOVZDI2PDIrm,       0 },
514     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
515     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
516     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
517     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
518     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
519     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
520     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
521     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
522     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
523     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
524     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
525     { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
526     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
527     { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
528     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
529     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
530     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
531     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
532     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
535     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
536     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
537     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
538     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
539     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
540     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
541     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
544     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
545     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
546     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
547     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
548     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
549     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
550     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
551     { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
552     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
553     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
554     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
555     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
556     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
559     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
560     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
561     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
562     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
563     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
564     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
565     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
566     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
567     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
568     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
569     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
570     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
571     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
572     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
573     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
574     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
575     { X86::RORX32ri,        X86::RORX32mi,            0 },
576     { X86::RORX64ri,        X86::RORX64mi,            0 },
577     { X86::SARX32rr,        X86::SARX32rm,            0 },
578     { X86::SARX64rr,        X86::SARX64rm,            0 },
579     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
580     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
581     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
582     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
583     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
584     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
585     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
599     { X86::ADC32rr,         X86::ADC32rm,       0 },
600     { X86::ADC64rr,         X86::ADC64rm,       0 },
601     { X86::ADD16rr,         X86::ADD16rm,       0 },
602     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
603     { X86::ADD32rr,         X86::ADD32rm,       0 },
604     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
605     { X86::ADD64rr,         X86::ADD64rm,       0 },
606     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
607     { X86::ADD8rr,          X86::ADD8rm,        0 },
608     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
609     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
610     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
611     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
612     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
613     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
614     { X86::AND16rr,         X86::AND16rm,       0 },
615     { X86::AND32rr,         X86::AND32rm,       0 },
616     { X86::AND64rr,         X86::AND64rm,       0 },
617     { X86::AND8rr,          X86::AND8rm,        0 },
618     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
619     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
620     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
621     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
622     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
623     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
624     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
625     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
626     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
627     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
628     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
629     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
630     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
631     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
632     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
633     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
634     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
635     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
636     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
637     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
638     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
639     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
640     { X86::CMOVE64rr,       X86
641     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
642     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
643     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
644     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
645     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
646     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
647     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
648     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
649     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
650     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
651     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
652     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
653     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
654     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
655     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
656     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
657     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
658     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
659     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
660     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
661     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
662     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
663     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
664     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
665     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
666     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
667     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
668     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
669     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
670     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
671     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
672     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
673     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
674     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
675     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
676     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
677     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
678     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
679     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
680     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
681     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
682     { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
683     { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
684     { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
685     { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
686     { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
687     { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
688     { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
689     { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
690     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
691     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
692     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
693     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
694     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
695     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
696     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
697     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
698     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
699     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
700     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
701     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
702     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
703     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
704     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
705     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
706     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
707     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
708     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
709     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
710     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
711     { X86::MINSDrr,         X86::MINSDrm,       0 },
712     { X86::MINSSrr,         X86::MINSSrm,       0 },
713     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
714     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
715     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
716     { X86::MULSDrr,         X86::MULSDrm,       0 },
717     { X86::MULSSrr,         X86::MULSSrm,       0 },
718     { X86::OR16rr,          X86::OR16rm,        0 },
719     { X86::OR32rr,          X86::OR32rm,        0 },
720     { X86::OR64rr,          X86::OR64rm,        0 },
721     { X86::OR8rr,           X86::OR8rm,         0 },
722     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
723     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
724     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
725     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
726     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
727     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
728     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
729     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
730     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
731     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
732     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
733     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
734     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
735     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
736     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
737     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
738     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
739     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
740     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
741     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
742     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
743     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
744     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
745     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
746     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
747     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
748     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
749     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
750     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
751     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
752     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
753     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
754     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
755     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
756     { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
757     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
758     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
759     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
760     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
761     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
762     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
763     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
764     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
765     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
766     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
767     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
768     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
769     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
770     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
771     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
772     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
773     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
774     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
775     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
776     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
777     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
778     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
779     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
780     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
781     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
782     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
783     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
784     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
785     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
786     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
787     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
788     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
789     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
790     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
791     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
792     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
793     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
794     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
795     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
796     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
797     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
798     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
799     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
800     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
801     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
802     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
803     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
804     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
805     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
806     { X86::SBB32rr,         X86::SBB32rm,       0 },
807     { X86::SBB64rr,         X86::SBB64rm,       0 },
808     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
809     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
810     { X86::SUB16rr,         X86::SUB16rm,       0 },
811     { X86::SUB32rr,         X86::SUB32rm,       0 },
812     { X86::SUB64rr,         X86::SUB64rm,       0 },
813     { X86::SUB8rr,          X86::SUB8rm,        0 },
814     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
815     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
816     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
817     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
819     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
820     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
821     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
822     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
823     { X86::XOR16rr,         X86::XOR16rm,       0 },
824     { X86::XOR32rr,         X86::XOR32rm,       0 },
825     { X86::XOR64rr,         X86::XOR64rm,       0 },
826     { X86::XOR8rr,          X86::XOR8rm,        0 },
827     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
828     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
830     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
831     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
832     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
833     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
834     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
835     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
836     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
837     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
838     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
839     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
840     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
841     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
842     { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQXrm,      0 },
843     { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       0 },
844     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
845     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
846     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
847     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
848     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
849     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
850     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
851     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
852     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
853     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
854     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
855     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
856     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
857     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
858     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
859     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
860     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
861     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
862     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
863     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
864     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
865     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
866     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
867     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
868     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
869     { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
870     { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
871     { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
872     { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
873     { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
874     { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
875     { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
876     { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
877     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
878     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
879     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
880     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
881     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
882     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
883     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
884     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
885     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
886     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
887     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
888     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
889     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
890     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
891     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
892     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
893     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
894     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
895     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
896     { X86::VORPDrr,           X86::VORPDrm,            0 },
897     { X86::VORPSrr,           X86::VORPSrm,            0 },
898     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
899     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
900     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
901     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
902     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
903     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
904     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
905     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
906     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
907     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
908     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
909     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
910     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
911     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
912     { X86::VPANDrr,           X86::VPANDrm,            0 },
913     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
914     { X86X86::VPAVGWrm,           0 },
915     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
916     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
917     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
918     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
919     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
920     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
921     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
922     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
923     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
924     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
925     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
926     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
927     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
928     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
929     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
930     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
931     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
932     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
933     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
934     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
935     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
936     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
937     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
938     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
939     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
940     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
941     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
942     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
943     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
944     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
945     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
946     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
947     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
948     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
949     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
950     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
951     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
952     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
953     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
954     { X86::VPORrr,            X86::VPORrm,             0 },
955     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
956     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
957     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
958     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
959     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
960     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
961     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
962     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
963     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
964     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
965     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
966     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
967     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
968     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
969     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
970     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
971     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
972     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
973     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
974     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
975     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
976     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
977     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
978     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
979     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
980     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
981     { X86::VPXORrr,           X86::VPXORrm,            0 },
982     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
983     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
984     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
985     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
986     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
987     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
988     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
989     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
990     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
991     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
992     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
993     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
995     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
996     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
997     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
998     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
999     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
1000     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
1001     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
1002     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
1003     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
1004     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
1005     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
1006     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
1007     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
1008     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
1009     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
1010     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
1011     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
1012     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
1013     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
1014     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
1015     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
1016     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
1017     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
1018     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
1019     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
1020     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
1021     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
1022     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
1023     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
1024     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
1025     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
1026     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
1027     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
1028     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
1029     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
1030     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
1031     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
1032     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
1033     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
1034     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
1035     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
1036     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
1038     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
1039     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
1040     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
1041     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
1042     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
1043     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
1044     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
1045     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
1046     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
1047     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
1048     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
1049     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
1050     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
1051     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
1052     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
1053     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
1054     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
1055     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
1056     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
1057     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
1058     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
1059     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
1060     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
1061     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
1062     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
1063     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
1064     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
1065     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
1066     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
1067     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
1068     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
1069     { X86::VPERMPDYri,        X86::VPERMPDYmi,         0 },
1070     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
1071     { X86::VPERMQYri,         X86::VPERMQYmi,          0 },
1072     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
1073     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
1074     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
1075     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
1076     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
1077     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
1078     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
1079     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
1080     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
1081     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
1082     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
1083     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
1084     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
1085     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
1086     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
1087     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
1088     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
1089     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
1090     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
1091     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
1092     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
1093     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
1094     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
1095     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
1096     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
1097     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
1098     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
1099     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
1100     { X86::VPORYrr,           X86::VPORYrm,            0 },
1101     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
1102     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
1103     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
1104     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
1105     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
1106     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
1107     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
1108     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
1109     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
1110     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
1111     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
1112     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
1113     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
1114     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
1115     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
1116     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
1117     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
1118     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
1119     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
1120     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
1121     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
1122     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
1123     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
1124     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
1125     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
1126     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
1127     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
1128     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
1129     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
1130     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
1131     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
1132     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
1133     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
1134     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
1135     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
1136     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
1137     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
1141     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0           },
1142     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0           },
1143     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_16 },
1144     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_16 },
1145     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_32 },
1146     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_32 },
1147     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0           },
1148     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0           },
1149     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_16 },
1150     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_16 },
1151     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_32 },
1152     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_32 },
1153     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0           },
1154     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0           },
1155     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_16 },
1156     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_16 },
1157     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_32 },
1158     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_32 },
1159     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0           },
1160     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0           },
1161     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_16 },
1162     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_16 },
1163     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_32 },
1164     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_32 },
1165     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_16 },
1166     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_16 },
1167     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_32 },
1168     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_32 },
1169     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_16 },
1170     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_16 },
1171     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_32 },
1172     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_32 },
1175     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1176     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1177     { X86::MULX32rr,          X86::MULX32rm,            0 },
1178     { X86::MULX64rr,          X86::MULX64rm,            0 },
1179     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1180     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1181     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1182     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1197     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         0 },
1198     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         0 },
1199     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         0 },
1200     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         0 },
1201     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         0 },
1202     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         0 },
1203     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     0 },
1204     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     0 },
1206     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_16 },
1207     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_16 },
1208     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_16 },
1209     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_16 },
1210     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_16 },
1211     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_16 },
1212     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_32 },
1213     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_32 },
1214     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_32 },
1215     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_32 },
1216     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_32 },
1217     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_32 },
1219     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        0 },
1220     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        0 },
1221     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        0 },
1222     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        0 },
1223     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        0 },
1224     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        0 },
1225     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    0 },
1226     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    0 },
1228     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_16 },
1229     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_16 },
1230     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_16 },
1231     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_16 },
1232     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_16 },
1233     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_16 },
1234     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_32 },
1235     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_32 },
1236     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_32 },
1237     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_32 },
1238     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_32 },
1239     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_32 },
1241     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         0 },
1242     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         0 },
1243     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         0 },
1244     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         0 },
1245     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         0 },
1246     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         0 },
1247     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     0 },
1248     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     0 },
1250     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_16 },
1251     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_16 },
1252     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_16 },
1253     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_16 },
1254     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_16 },
1255     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_16 },
1256     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_32 },
1257     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_32 },
1258     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_32 },
1259     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_32 },
1260     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_32 },
1261     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_32 },
1263     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        0 },
1264     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        0 },
1265     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        0 },
1266     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        0 },
1267     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        0 },
1268     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        0 },
1269     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    0 },
1270     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    0 },
1272     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_16 },
1273     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_16 },
1274     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_16 },
1275     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_16 },
1276     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_16 },
1277     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_16 },
1278     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_32 },
1279     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_32 },
1280     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_32 },
1281     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_32 },
1282     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_32 },
1283     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_32 },
1285     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_16 },
1286     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_16 },
1287     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_16 },
1288     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_16 },
1289     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_16 },
1290     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_16 },
1291     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_32 },
1292     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_32 },
1293     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_32 },
1294     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_32 },
1295     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_32 },
1296     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_32 },
1298     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_16 },
1299     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_16 },
1300     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_16 },
1301     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_16 },
1302     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_16 },
1303     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_16 },
1304     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_32 },
1305     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_32 },
1306     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_32 },
1307     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_32 },
1308     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_32 },
1309     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_32 },
1312     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1313     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1314     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1315     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1316     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1317     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1318     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1319     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1320     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1321     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1322     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1323     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1324     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1325     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1326     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1327     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1328     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1329     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1330     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1331     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1332     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1333     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1334     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1335     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1336     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1337     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1338     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1339     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1340     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1341     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1342     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1343     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1379   case X86::MOVSX16rr8:
1380   case X86::MOVZX16rr8:
1381   case X86::MOVSX32rr8:
1382   case X86::MOVZX32rr8:
1383   case X86::MOVSX64rr8:
1384   case X86::MOVZX64rr8:
1389   case X86::MOVSX32rr16:
1390   case X86::MOVZX32rr16:
1391   case X86::MOVSX64rr16:
1392   case X86::MOVZX64rr16:
1393   case X86::MOVSX64rr32:
1394   case X86::MOVZX64rr32: {
1402     case X86::MOVSX16rr8:
1403     case X86::MOVZX16rr8:
1404     case X86::MOVSX32rr8:
1405     case X86::MOVZX32rr8:
1406     case X86::MOVSX64rr8:
1407     case X86::MOVZX64rr8:
1408       SubIdx = X86::sub_8bit;
1410     case X86::MOVSX32rr16:
1411     case X86::MOVZX32rr16:
1412     case X86::MOVSX64rr16:
1413     case X86::MOVZX64rr16:
1414       SubIdx = X86::sub_16bit;
1416     case X86::MOVSX64rr32:
1417     case X86::MOVZX64rr32:
1418       SubIdx = X86::sub_32bit;
1446   case X86::MOV8rm:
1447   case X86::MOV16rm:
1448   case X86::MOV32rm:
1449   case X86::MOV64rm:
1450   case X86::LD_Fp64m:
1451   case X86::MOVSSrm:
1452   case X86::MOVSDrm:
1453   case X86::MOVAPSrm:
1454   case X86::MOVAPDrm:
1455   case X86::MOVDQArm:
1456   case X86::VMOVSSrm:
1457   case X86::VMOVSDrm:
1458   case X86::VMOVAPSrm:
1459   case X86::VMOVAPDrm:
1460   case X86::VMOVDQArm:
1461   case X86::VMOVAPSYrm:
1462   case X86::VMOVAPDYrm:
1463   case X86::VMOVDQAYrm:
1464   case X86::MMX_MOVD64rm:
1465   case X86::MMX_MOVQ64rm:
1473   case X86::MOV8mr:
1474   case X86::MOV16mr:
1475   case X86::MOV32mr:
1476   case X86::MOV64mr:
1477   case X86::ST_FpP64m:
1478   case X86::MOVSSmr:
1479   case X86::MOVSDmr:
1480   case X86::MOVAPSmr:
1481   case X86::MOVAPDmr:
1482   case X86::MOVDQAmr:
1483   case X86::VMOVSSmr:
1484   case X86::VMOVSDmr:
1485   case X86::VMOVAPSmr:
1486   case X86::VMOVAPDmr:
1487   case X86::VMOVDQAmr:
1488   case X86::VMOVAPSYmr:
1489   case X86::VMOVAPDYmr:
1490   case X86::VMOVDQAYmr:
1491   case X86::MMX_MOVD64mr:
1492   case X86::MMX_MOVQ64mr:
1493   case X86::MMX_MOVNTQmr:
1523     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1525       return MI->getOperand(X86::AddrNumOperands).getReg();
1543 /// X86::MOVPC32r.
1552     if (DefMI->getOpcode() != X86::MOVPC32r)
1565   case X86::MOV8rm:
1566   case X86::MOV16rm:
1567   case X86::MOV32rm:
1568   case X86::MOV64rm:
1569   case X86::LD_Fp64m:
1570   case X86::MOVSSrm:
1571   case X86::MOVSDrm:
1572   case X86::MOVAPSrm:
1573   case X86::MOVUPSrm:
1574   case X86::MOVAPDrm:
1575   case X86::MOVDQArm:
1576   case X86::MOVDQUrm:
1577   case X86::VMOVSSrm:
1578   case X86::VMOVSDrm:
1579   case X86::VMOVAPSrm:
1580   case X86::VMOVUPSrm:
1581   case X86::VMOVAPDrm:
1582   case X86::VMOVDQArm:
1583   case X86::VMOVDQUrm:
1584   case X86::VMOVAPSYrm:
1585   case X86::VMOVUPSYrm:
1586   case X86::VMOVAPDYrm:
1587   case X86::VMOVDQAYrm:
1588   case X86::VMOVDQUYrm:
1589   case X86::MMX_MOVD64rm:
1590   case X86::MMX_MOVQ64rm:
1591   case X86::FsVMOVAPSrm:
1592   case X86::FsVMOVAPDrm:
1593   case X86::FsMOVAPSrm:
1594   case X86::FsMOVAPDrm: {
1601       if (BaseReg == 0 || BaseReg == X86::RIP)
1613   case X86::LEA32r:
1614   case X86::LEA64r: {
1654       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1658       if (MO.getReg() == X86::EFLAGS) {
1679       if ((*SI)->isLiveIn(X86::EFLAGS))
1690       return !MBB.isLiveIn(X86::EFLAGS);
1702       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1704       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1733   case X86::MOV8r0:
1734   case X86::MOV16r0:
1735   case X86::MOV32r0:
1736   case X86::MOV64r0: {
1740       case X86::MOV8r0:  Opc = X86::MOV8ri;  break;
1741       case X86::MOV16r0: Opc = X86::MOV16ri; break;
1742       case X86::MOV32r0: Opc = X86::MOV32ri; break;
1743       case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1768         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1791     ? X86::LEA64_32r : X86::LEA32r;
1793   unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1794   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1802   // least on modern x86 machines).
1803   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1806     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1813   case X86::SHL16ri: {
1819   case X86::INC16r:
1820   case X86::INC64_16r:
1823   case X86::DEC16r:
1824   case X86::DEC64_16r:
1827   case X86::ADD16ri:
1828   case X86::ADD16ri8:
1829   case X86::ADD16ri_DB:
1830   case X86::ADD16ri8_DB:
1833   case X86::ADD16rr:
1834   case X86::ADD16rr_DB: {
1844       leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1847       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1850         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1864     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1882 /// three-address instruction on demand.  This allows the X86 target (for
1908   case X86::SHUFPSrri: {
1916     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1920   case X86::SHUFPDrri: {
1932     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1936   case X86::SHL64ri: {
1946                                            &X86::GR64_NOSPRegClass))
1949     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1954   case X86::SHL32ri: {
1964                                            &X86::GR32_NOSPRegClass))
1967     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1973   case X86::SHL16ri: {
1982     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1996     case X86::INC64r:
1997     case X86::INC32r:
1998     case X86::INC64_32r: {
2000       unsigned Opc = MIOpc == X86X86::LEA64r
2001         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2002       const TargetRegisterClass *RC = MIOpc == X86::INC64r ?
2003         (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
2004         (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
2015     case X86::INC16r:
2016     case X86::INC64_16r:
2020       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2023     case X86::DEC64r:
2024     case X86::DEC32r:
2025     case X86::DEC64_32r: {
2027       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2028         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2029       const TargetRegisterClass *RC = MIOpc == X86::DEC64r ?
2030         (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
2031         (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
2041     case X86::DEC16r:
2042     case X86::DEC64_16r:
2046       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2049     case X86::ADD64rr:
2050     case X86::ADD64rr_DB:
2051     case X86::ADD32rr:
2052     case X86::ADD32rr_DB: {
2056       if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
2057         Opc = X86::LEA64r;
2058         RC = &X86::GR64_NOSPRegClass;
2060         Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2061         RC = &X86::GR32_NOSPRegClass;
2087     case X86::ADD16rr:
2088     case X86::ADD16rr_DB: {
2094       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2108     case X86::ADD64ri32:
2109     case X86::ADD64ri8:
2110     case X86::ADD64ri32_DB:
2111     case X86::ADD64ri8_DB:
2113       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2117     case X86::ADD32ri:
2118     case X86::ADD32ri8:
2119     case X86::ADD32ri_DB:
2120     case X86::ADD32ri8_DB: {
2122       unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2128     case X86::ADD16ri:
2129     case X86::ADD16ri8:
2130     case X86::ADD16ri_DB:
2131     case X86::ADD16ri8_DB:
2135       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2162   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2163   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2164   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2165   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2166   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2167   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2172     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2173     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2174     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2175     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2176     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2177     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2189   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2190   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2191   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2192   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2193   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2194   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2195   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2196   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2197   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2198   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2199   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2200   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2201   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2202   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2203   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2204   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2208     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2209     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2210     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2211     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2212     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2213     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2214     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2215     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2216     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2217     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2218     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2219     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2220     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2221     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2222     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2223     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2224     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2225     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2226     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2227     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2228     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2229     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2230     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2231     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2232     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2233     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2234     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2235     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2236     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2237     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2238     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2239     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2240     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2241     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2242     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2243     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2244     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2245     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2246     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2247     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2248     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2249     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2250     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2251     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2252     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2253     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2254     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2255     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2270 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2272   default: return X86::COND_INVALID;
2273   case X86::JE_4:  return X86::COND_E;
2274   case X86::JNE_4: return X86::COND_NE;
2275   case X86::JL_4:  return X86::COND_L;
2276   case X86::JLE_4: return X86::COND_LE;
2277   case X86::JG_4:  return X86::COND_G;
2278   case X86::JGE_4: return X86::COND_GE;
2279   case X86::JB_4:  return X86::COND_B;
2280   case X86::JBE_4: return X86::COND_BE;
2281   case X86::JA_4:  return X86::COND_A;
2282   case X86::JAE_4: return X86::COND_AE;
2283   case X86::JS_4:  return X86::COND_S;
2284   case X86::JNS_4: return X86::COND_NS;
2285   case X86::JP_4:  return X86::COND_P;
2286   case X86::JNP_4: return X86::COND_NP;
2287   case X86::JO_4:  return X86::COND_O;
2288   case X86::JNO_4: return X86::COND_NO;
2293 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2295   default: return X86::COND_INVALID;
2296   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2297   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2298   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2299   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2300   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2301   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2302   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2303   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2304   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2305   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2306   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2307   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2308   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2309   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2310   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2311   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2316 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2318   default: return X86::COND_INVALID;
2319   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2320   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2321     return X86::COND_A;
2322   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2323   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2324     return X86::COND_AE;
2325   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2326   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2327     return X86::COND_B;
2328   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2329   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2330     return X86::COND_BE;
2331   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2332   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2333     return X86::COND_E;
2334   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2335   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2336     return X86::COND_G;
2337   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2338   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2339     return X86::COND_GE;
2340   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2341   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2342     return X86::COND_L;
2343   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2344   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2345     return X86::COND_LE;
2346   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2347   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2348     return X86::COND_NE;
2349   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2350   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2351     return X86::COND_NO;
2352   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2353   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2354     return X86::COND_NP;
2355   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2356   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2357     return X86::COND_NS;
2358   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
2359   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
2360     return X86::COND_O;
2361   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
2362   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
2363     return X86::COND_P;
2364   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
2365   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
2366     return X86::COND_S;
2370 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2373   case X86::COND_E:  return X86::JE_4;
2374   case X86::COND_NE: return X86::JNE_4;
2375   case X86::COND_L:  return X86::JL_4;
2376   case X86::COND_LE: return X86::JLE_4;
2377   case X86X86::JG_4;
2378   case X86::COND_GE: return X86::JGE_4;
2379   case X86::COND_B:  return X86::JB_4;
2380   case X86::COND_BE: return X86::JBE_4;
2381   case X86::COND_A:  return X86::JA_4;
2382   case X86::COND_AE: return X86::JAE_4;
2383   case X86::COND_S:  return X86::JS_4;
2384   case X86::COND_NS: return X86::JNS_4;
2385   case X86::COND_P:  return X86::JP_4;
2386   case X86::COND_NP: return X86::JNP_4;
2387   case X86::COND_O:  return X86::JO_4;
2388   case X86::COND_NO: return X86::JNO_4;
2394 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2397   case X86::COND_E:  return X86::COND_NE;
2398   case X86::COND_NE: return X86::COND_E;
2399   case X86::COND_L:  return X86::COND_GE;
2400   case X86::COND_LE: return X86::COND_G;
2401   case X86::COND_G:  return X86::COND_LE;
2402   case X86::COND_GE: return X86::COND_L;
2403   case X86::COND_B:  return X86::COND_AE;
2404   case X86::COND_BE: return X86::COND_A;
2405   case X86::COND_A:  return X86::COND_BE;
2406   case X86::COND_AE: return X86::COND_B;
2407   case X86::COND_S:  return X86::COND_NS;
2408   case X86::COND_NS: return X86::COND_S;
2409   case X86::COND_P:  return X86::COND_NP;
2410   case X86::COND_NP: return X86::COND_P;
2411   case X86::COND_O:  return X86::COND_NO;
2412   case X86::COND_NO: return X86::COND_O;
2419 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2421   default: return X86::COND_INVALID;
2422   case X86::COND_E:  return X86::COND_E;
2423   case X86::COND_NE: return X86::COND_NE;
2424   case X86::COND_L:  return X86::COND_G;
2425   case X86::COND_LE: return X86::COND_GE;
2426   case X86::COND_G:  return X86::COND_L;
2427   case X86::COND_GE: return X86::COND_LE;
2428   case X86::COND_B:  return X86::COND_A;
2429   case X86::COND_BE: return X86::COND_AE;
2430   case X86::COND_A:  return X86::COND_B;
2431   case X86::COND_AE: return X86::COND_BE;
2437 static unsigned getSETFromCond(X86::CondCode CC,
2440     { X86::SETAr,  X86::SETAm  },
2441     { X86::SETAEr, X86::SETAEm },
2442     { X86::SETBr,  X86::SETBm  },
2443     { X86::SETBEr, X86::SETBEm },
2444     { X86::SETEr,  X86::SETEm  },
2445     { X86::SETGr,  X86::SETGm  },
2446     { X86::SETGEr, X86::SETGEm },
2447     { X86::SETLr,  X86::SETLm  },
2448     { X86::SETLEr, X86::SETLEm },
2449     { X86::SETNEr, X86::SETNEm },
2450     { X86::SETNOr, X86::SETNOm },
2451     { X86::SETNPr, X86::SETNPm },
2452     { X86::SETNSr, X86::SETNSm },
2453     { X86::SETOr,  X86::SETOm  },
2454     { X86::SETPr,  X86::SETPm  },
2455     { X86::SETSr,  X86::SETSm  }
2464 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes,
2467     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
2468     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2469     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
2470     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2471     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
2472     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
2473     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2474     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
2475     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2476     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2477     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2478     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2479     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2480     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
2481     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
2482     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
2483     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
2484     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2485     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
2486     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2487     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
2488     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
2489     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2490     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
2491     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2492     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2493     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2494     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2495     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2496     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
2497     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
2498     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
2547     if (I->getOpcode() == X86::JMP_4) {
2577     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2578     if (BranchCode == X86::COND_INVALID)
2609         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2639     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2646     if ((OldBranchCode == X86::COND_NP &&
2647          BranchCode == X86::COND_E) ||
2648         (OldBranchCode == X86::COND_E &&
2649          BranchCode == X86::COND_NP))
2650       BranchCode = X86::COND_NP_OR_E;
2651     else if ((OldBranchCode == X86::COND_P &&
2652               BranchCode == X86::COND_NE) ||
2653              (OldBranchCode == X86::COND_NE &&
2654               BranchCode == X86::COND_P))
2655       BranchCode = X86::COND_NE_OR_P;
2674     if (I->getOpcode() != X86::JMP_4 &&
2675         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2694          "X86 branch conditions have one component!");
2699     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2705   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2707   case X86::COND_NP_OR_E:
2709     BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2711     BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2714   case X86::COND_NE_OR_P:
2716     BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2718     BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2729     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2746   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2757   if (X86::GR16RegClass.hasSubClassEq(RC) ||
2758       X86::GR32RegClass.hasSubClassEq(RC) ||
2759       X86::GR64RegClass.hasSubClassEq(RC)) {
2779    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
2787   return X86::GR8_ABCD_HRegClass.contains(Reg);
2798   if (X86::GR64RegClass.contains(DestReg)) {
2799     if (X86::VR128RegClass.contains(SrcReg))
2801       return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
2802     if (X86::VR64RegClass.contains(SrcReg))
2804       return X86::MOVSDto64rr;
2805   } else if (X86::GR64RegClass.contains(SrcReg)) {
2807     if (X86::VR128RegClass.contains(DestReg))
2808       return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
2810     if (X86::VR64RegClass.contains(DestReg))
2811       return X86::MOV64toSDrr;
2817   if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2819     return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
2821   if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2823     return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
2835   if (X86::GR64RegClass.contains(DestReg, SrcReg))
2836     Opc = X86::MOV64rr;
2837   else if (X86
2838     Opc = X86::MOV32rr;
2839   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2840     Opc = X86::MOV16rr;
2841   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2842     // Copying to or from a physical H register on x86-64 requires a NOREX
2846       Opc = X86::MOV8rr_NOREX;
2848       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2851       Opc = X86::MOV8rr;
2852   } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2853     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2854   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2855     Opc = X86::VMOVAPSYrr;
2856   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2857     Opc = X86::MMX_MOVQ64rr;
2870   if (SrcReg == X86::EFLAGS) {
2871     if (X86::GR64RegClass.contains(DestReg)) {
2872       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2873       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2876     if (X86::GR32RegClass.contains(DestReg)) {
2877       BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2878       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2882   if (DestReg == X86::EFLAGS) {
2883     if (X86::GR64RegClass.contains(SrcReg)) {
2884       BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2886       BuildMI(MBB, MI, DL, get(X86::POPF64));
2889     if (X86::GR32RegClass.contains(SrcReg)) {
2890       BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2892       BuildMI(MBB, MI, DL, get(X86::POPF32));
2912     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2914       // Copying to or from a physical H register on x86-64 requires a NOREX
2916       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2917         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2918     return load ? X86::MOV8rm : X86::MOV8mr;
2920     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2921     return load ? X86::MOV16rm : X86::MOV16mr;
2923     if (X86::GR32RegClass.hasSubClassEq(RC))
2924       return load ? X86::MOV32rm : X86::MOV32mr;
2925     if (X86::FR32RegClass.hasSubClassEq(RC))
2927         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2928         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2929     if (X86::RFP32RegClass.hasSubClassEq(RC))
2930       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2933     if (X86::GR64RegClass.hasSubClassEq(RC))
2934       return load ? X86::MOV64rm : X86::MOV64mr;
2935     if (X86::FR64RegClass.hasSubClassEq(RC))
2937         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2938         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2939     if (X86::VR64RegClass.hasSubClassEq(RC))
2940       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2941     if (X86::RFP64RegClass.hasSubClassEq(RC))
2942       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2945     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2946     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2948     assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2952         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2953         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
2956         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2957         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2960     assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2963       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2965       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
3059   case X86::CMP64ri32:
3060   case X86::CMP64ri8:
3061   case X86::CMP32ri:
3062   case X86::CMP32ri8:
3063   case X86::CMP16ri:
3064   case X86::CMP16ri8:
3065   case X86::CMP8ri:
3072   case X86::SUB64rm:
3073   case X86::SUB32rm:
3074   case X86::SUB16rm:
3075   case X86::SUB8rm:
3081   case X86::SUB64rr:
3082   case X86::SUB32rr:
3083   case X86::SUB16rr:
3084   case X86::SUB8rr:
3090   case X86::SUB64ri32:
3091   case X86::SUB64ri8:
3092   case X86::SUB32ri:
3093   case X86::SUB32ri8:
3094   case X86::SUB16ri:
3095   case X86::SUB16ri8:
3096   case X86::SUB8ri:
3102   case X86::CMP64rr:
3103   case X86::CMP32rr:
3104   case X86::CMP16rr:
3105   case X86::CMP8rr:
3111   case X86::TEST8rr:
3112   case X86::TEST16rr:
3113   case X86::TEST32rr:
3114   case X86::TEST64rr:
3135   if (((FlagI->getOpcode() == X86::CMP64rr &&
3136         OI->getOpcode() == X86::SUB64rr) ||
3137        (FlagI->getOpcode() == X86::CMP32rr &&
3138         OI->getOpcode() == X86::SUB32rr)||
3139        (FlagI->getOpcode() == X86::CMP16rr &&
3140         OI->getOpcode() == X86::SUB16rr)||
3141        (FlagI->getOpcode() == X86::CMP8rr &&
3142         OI->getOpcode() == X86::SUB8rr)) &&
3149   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3150         OI->getOpcode() == X86::SUB64ri32) ||
3151        (FlagI->getOpcode() == X86::CMP64ri8 &&
3152         OI->getOpcode() == X86::SUB64ri8) ||
3153        (FlagI->getOpcode() == X86::CMP32ri &&
3154         OI->getOpcode() == X86::SUB32ri) ||
3155        (FlagI->getOpcode() == X86::CMP32ri8 &&
3156         OI->getOpcode() == X86::SUB32ri8) ||
3157        (FlagI->getOpcode() == X86::CMP16ri &&
3158         OI->getOpcode() == X86::SUB16ri) ||
3159        (FlagI->getOpcode() == X86::CMP16ri8 &&
3160         OI->getOpcode() == X86::SUB16ri8) ||
3161        (FlagI->getOpcode() == X86::CMP8ri &&
3162         OI->getOpcode() == X86::SUB8ri)) &&
3174   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3175   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3176   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3177   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3178   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3179   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3180   case X86::DEC64_32r: case X86::DEC64_16r:
3181   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3182   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3183   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3184   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3185   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3186   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3187   case X86::INC64_32r: case X86::INC64_16r:
3188   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3189   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3190   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3191   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3192   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3193   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3194   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3195   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3196   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3197   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3198   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3199   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3200   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3201   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3202   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3203   case X86::ANDN32rr:  case X86::ANDN32rm:
3204   case X86::ANDN64rr:  case X86::ANDN64rm:
3220   case X86::SUB64ri32:
3221   case X86::SUB64ri8:
3222   case X86::SUB32ri:
3223   case X86::SUB32ri8:
3224   case X86::SUB16ri:
3225   case X86::SUB16ri8:
3226   case X86::SUB8ri:
3227   case X86::SUB64rm:
3228   case X86::SUB32rm:
3229   case X86::SUB16rm:
3230   case X86::SUB8rm:
3231   case X86::SUB64rr:
3232   case X86::SUB32rr:
3233   case X86::SUB16rr:
3234   case X86::SUB8rr: {
3240     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
3241     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
3242     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
3243     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
3244     case X86X86::CMP64rr;   break;
3245     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
3246     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
3247     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
3248     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3249     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
3250     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
3251     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
3252     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
3253     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
3254     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
3259     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3260         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3304     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3305         Instr->readsRegister(X86::EFLAGS, TRI)) {
3311       if (!Movr0Inst && (Instr->getOpcode() == X86::MOV8r0 ||
3312            Instr->getOpcode() == X86::MOV16r0 ||
3313            Instr->getOpcode() == X86::MOV32r0 ||
3314            Instr->getOpcode() == X86::MOV64r0) &&
3315           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3341     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3342     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3353     X86::CondCode OldCC;
3361         if (OldCC != X86::COND_INVALID)
3364           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3366       if (OldCC == X86::COND_INVALID) return false;
3371       case X86::COND_A: case X86::COND_AE:
3372       case X86::COND_B: case X86::COND_BE:
3373       case X86::COND_G: case X86::COND_GE:
3374       case X86::COND_L: case X86::COND_LE:
3375       case X86::COND_O: case X86::COND_NO:
3383       X86::CondCode NewCC = getSwappedCondition(OldCC);
3384       if (NewCC == X86::COND_INVALID) return false;
3404     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3417       if ((*SI)->isLiveIn(X86::EFLAGS))
3433          Sub->getOperand(LastOperand).getReg() == X86::EFLAGS &&
3546   case X86::SETB_C8r:
3547     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
3548   case X86::SETB_C16r:
3549     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
3550   case X86::SETB_C32r:
3551     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
3552   case X86::SETB_C64r:
3553     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
3554   case X86::V_SET0:
3555   case X86::FsFLD0SS:
3556   case X86::FsFLD0SD:
3557     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
3558   case X86::AVX_SET0:
3560     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
3561   case X86::V_SETALLONES:
3562     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
3563   case X86::AVX2_SETALLONES:
3564     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
3565   case X86::TEST8ri_NOREX:
3566     MI->setDesc(get(X86::TEST8ri));
3580   MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
3665   if (MI->getOpcode() == X86::ADD32ri &&
3683     case X86::MOV64r0: Opc = X86::MOV64mi32; break;
3684     case X86::MOV32r0: Opc = X86::MOV32mi;   break;
3685     case X86::MOV16r0: Opc = X86::MOV16mi;   break;
3686     case X86::MOV8r0:  Opc = X86::MOV8mi;    break;
3718           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
3725           Opcode = X86::MOV32rm;
3742                                                    X86::sub_32bit));
3744           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
3774   case X86::CVTSI2SSrr:
3775   case X86::CVTSI2SS64rr:
3776   case X86::CVTSI2SDrr:
3777   case X86::CVTSI2SD64rr:
3778   case X86::CVTSD2SSrr:
3779   case X86::Int_CVTSD2SSrr:
3780   case X86::CVTSS2SDrr:
3781   case X86::Int_CVTSS2SDrr:
3782   case X86::RCPSSr:
3783   case X86::RCPSSr_Int:
3784   case X86::ROUNDSDr:
3785   case X86::ROUNDSDr_Int:
3786   case X86::ROUNDSSr:
3787   case X86::ROUNDSSr_Int:
3788   case X86::RSQRTSSr:
3789   case X86::RSQRTSSr_Int:
3790   case X86::SQRTSSr:
3791   case X86::SQRTSSr_Int:
3793   case X86::VCVTSD2SSrr:
3794   case X86::Int_VCVTSD2SSrr:
3795   case X86::VCVTSS2SDrr:
3796   case X86::Int_VCVTSS2SDrr:
3797   case X86::VRCPSSr:
3798   case X86::VROUNDSDr:
3799   case X86::VROUNDSDr_Int:
3800   case X86::VROUNDSSr:
3801   case X86::VROUNDSSr_Int:
3802   case X86::VRSQRTSSr:
3803   case X86::VSQRTSSr:
3839   if (X86::VR128RegClass.contains(Reg)) {
3843     unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
3846   } else if (X86::VR256RegClass.contains(Reg)) {
3849     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
3850     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
3880     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
3881     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
3882     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
3883     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
3920     case X86::AVX2_SETALLONES:
3921     case X86::AVX_SET0:
3924     case X86::V_SET0:
3925     case X86::V_SETALLONES:
3928     case X86::FsFLD0SD:
3931     case X86::FsFLD0SS:
3941     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
3942     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
3943     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
3944     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
3957   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
3959   case X86::V_SET0:
3960   case X86::V_SETALLONES:
3961   case X86::AVX2_SETALLONES:
3962   case X86::AVX_SET0:
3963   case X86::FsFLD0SD:
3964   case X86::FsFLD0SS: {
3973     // x86-32 PIC requires a PIC base register for constant pools.
3977         PICBase = X86::RIP;
3990     if (Opc == X86::FsFLD0SS)
3992     else if (Opc == X86::FsFLD0SD)
3994     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
3999     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4013     if ((LoadMI->getOpcode() == X86::MOVSSrm ||
4014          LoadMI->getOpcode() == X86::VMOVSSrm) &&
4020     if ((LoadMI->getOpcode() == X86::MOVSDrm ||
4021          LoadMI->getOpcode() == X86::VMOVSDrm) &&
4030     for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
4047     case X86::TEST8rr:
4048     case X86::TEST16rr:
4049     case X86::TEST32rr:
4050     case X86::TEST64rr:
4052     case X86::ADD32ri:
4078     case X86::MOV8r0:
4079     case X86::MOV16r0:
4080     case X86::MOV32r0:
4081     case X86::MOV64r0: return true;
4119       RC == &X86::VR128RegClass &&
4125   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4131     if (i >= Index && i < Index + X86::AddrNumOperands)
4150       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
4182   case X86::CMP64ri32:
4183   case X86::CMP64ri8:
4184   case X86::CMP32ri:
4185   case X86::CMP32ri8:
4186   case X86::CMP16ri:
4187   case X86::CMP16ri8:
4188   case X86::CMP8ri: {
4195       case X86::CMP64ri8:
4196       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
4197       case X86::CMP32ri8:
4198       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
4199       case X86::CMP16ri8:
4200       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
4201       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
4248     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
4267         RC == &X86::VR128RegClass &&
4311         RC == &X86::VR128RegClass &&
4358   case X86::MOV8rm:
4359   case X86::MOV16rm:
4360   case X86::MOV32rm:
4361   case X86::MOV64rm:
4362   case X86::LD_Fp32m:
4363   case X86::LD_Fp64m:
4364   case X86::LD_Fp80m:
4365   case X86::MOVSSrm:
4366   case X86::MOVSDrm:
4367   case X86::MMX_MOVD64rm:
4368   case X86::MMX_MOVQ64rm:
4369   case X86::FsMOVAPSrm:
4370   case X86::FsMOVAPDrm:
4371   case X86::MOVAPSrm:
4372   case X86::MOVUPSrm:
4373   case X86::MOVAPDrm:
4374   case X86::MOVDQArm:
4375   case X86::MOVDQUrm:
4377   case X86::VMOVSSrm:
4378   case X86::VMOVSDrm:
4379   case X86::FsVMOVAPSrm:
4380   case X86::FsVMOVAPDrm:
4381   case X86::VMOVAPSrm:
4382   case X86::VMOVUPSrm:
4383   case X86::VMOVAPDrm:
4384   case X86::VMOVDQArm:
4385   case X86::VMOVDQUrm:
4386   case X86::VMOVAPSYrm:
4387   case X86::VMOVUPSYrm:
4388   case X86::VMOVAPDYrm:
4389   case X86::VMOVDQAYrm:
4390   case X86::VMOVDQUYrm:
4395   case X86::MOV8rm:
4396   case X86::MOV16rm:
4397   case X86::MOV32rm:
4398   case X86::MOV64rm:
4399   case X86::LD_Fp32m:
4400   case X86::LD_Fp64m:
4401   case X86::LD_Fp80m:
4402   case X86::MOVSSrm:
4403   case X86::MOVSDrm:
4404   case X86::MMX_MOVD64rm:
4405   case X86::MMX_MOVQ64rm:
4406   case X86::FsMOVAPSrm:
4407   case X86::FsMOVAPDrm:
4408   case X86::MOVAPSrm:
4409   case X86::MOVUPSrm:
4410   case X86::MOVAPDrm:
4411   case X86::MOVDQArm:
4412   case X86::MOVDQUrm:
4414   case X86::VMOVSSrm:
4415   case X86::VMOVSDrm:
4416   case X86::FsVMOVAPSrm:
4417   case X86::FsVMOVAPDrm:
4418   case X86::VMOVAPSrm:
4419   case X86::VMOVUPSrm:
4420   case X86::VMOVAPDrm:
4421   case X86::VMOVDQArm:
4422   case X86::VMOVDQUrm:
4423   case X86::VMOVAPSYrm:
4424   case X86::VMOVUPSYrm:
4425   case X86::VMOVAPDYrm:
4426   case X86::VMOVDQAYrm:
4427   case X86::VMOVDQUYrm:
4469   case X86::LD_Fp32m:
4470   case X86::LD_Fp64m:
4471   case X86::LD_Fp80m:
4472   case X86::MMX_MOVD64rm:
4473   case X86::MMX_MOVQ64rm:
4506   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
4507   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
4508   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
4518   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
4519            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
4530          "X86-64 PIC uses RIP relative addressing");
4540   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4550   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
4551   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
4552   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
4553   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
4554   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
4555   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
4556   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
4557   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
4558   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
4559   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
4560   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
4561   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
4562   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
4563   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
4565   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
4566   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
4567   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
4568   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
4569   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
4570   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
4571   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
4572   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
4573   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
4574   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
4575   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
4576   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
4577   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
4578   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
4580   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
4581   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
4582   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
4583   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
4584   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
4585   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
4590   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
4591   { X86::VANDNPSYrr,   X86X86::VPANDNYrr   },
4592   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
4593   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
4594   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
4595   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
4596   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
4597   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
4598   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
4599   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
4600   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
4601   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
4602   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
4603   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr }
4651   NopInst.setOpcode(X86::NOOP);
4657   case X86::DIVSDrm:
4658   case X86::DIVSDrm_Int:
4659   case X86::DIVSDrr:
4660   case X86::DIVSDrr_Int:
4661   case X86::DIVSSrm:
4662   case X86::DIVSSrm_Int:
4663   case X86::DIVSSrr:
4664   case X86::DIVSSrr_Int:
4665   case X86::SQRTPDm:
4666   case X86::SQRTPDr:
4667   case X86::SQRTPSm:
4668   case X86::SQRTPSr:
4669   case X86::SQRTSDm:
4670   case X86::SQRTSDm_Int:
4671   case X86::SQRTSDr:
4672   case X86::SQRTSDr_Int:
4673   case X86::SQRTSSm:
4674   case X86::SQRTSSm_Int:
4675   case X86::SQRTSSr:
4676   case X86::SQRTSSr_Int:
4678   case X86::VDIVSDrm:
4679   case X86::VDIVSDrm_Int:
4680   case X86::VDIVSDrr:
4681   case X86::VDIVSDrr_Int:
4682   case X86::VDIVSSrm:
4683   case X86::VDIVSSrm_Int:
4684   case X86::VDIVSSrr:
4685   case X86::VDIVSSrr_Int:
4686   case X86::VSQRTPDm:
4687   case X86::VSQRTPDr:
4688   case X86::VSQRTPSm:
4689   case X86::VSQRTPSr:
4690   case X86::VSQRTSDm:
4691   case X86::VSQRTSDm_Int:
4692   case X86::VSQRTSDr:
4693   case X86::VSQRTSSm:
4694   case X86::VSQRTSSm_Int:
4695   case X86::VSQRTSSr:
4710   /// global base register for x86-32.
4720              "X86-64 PIC uses RIP relative addressing");
4742         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
4748       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
4754         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
4763       return "X86 PIC Global Base Reg Initialization";
4806           case X86::TLS_base_addr32:
4807           case X86::TLS_base_addr64:
4841                                    is64Bit ? X86::RAX : X86::EAX)
4862                                                       ? &X86::GR64RegClass
4863                                                       : &X86::GR32RegClass);
4870                                    .addReg(is64Bit ? X86::RAX : X86::EAX);