Lines Matching full:x86
1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
243 if (Reg == 0 || Reg == X86::RIP) continue;
273 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
306 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
379 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
382 case X86::LEA64r:
383 case X86::LEA16r:
384 case X86::LEA32r:
386 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
388 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
391 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
392 case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
393 case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
394 case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
395 case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
396 case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
397 case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
398 case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
399 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
401 case X86::MOV16r0:
402 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
403 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
405 case X86::MOV64r0:
406 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
407 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
412 case X86::VMOVAPDrr:
413 case X86::VMOVAPDYrr:
414 case X86::VMOVAPSrr:
415 case X86::VMOVAPSYrr:
416 case X86::VMOVDQArr:
417 case X86::VMOVDQAYrr:
418 case X86::VMOVDQUrr:
419 case X86::VMOVDQUYrr:
420 case X86::VMOVUPDrr:
421 case X86::VMOVUPDYrr:
422 case X86::VMOVUPSrr:
423 case X86::VMOVUPSYrr: {
429 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
430 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
431 case X86::VMOVAPSrr: NewOpc = X86
432 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
433 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
434 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
435 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
436 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
437 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
438 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
439 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
440 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
446 case X86::VMOVSDrr:
447 case X86::VMOVSSrr: {
453 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
454 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
464 case X86::TAILJMPr64:
465 case X86::CALL64r:
466 case X86::CALL64pcrel32: {
475 case X86::EH_RETURN:
476 case X86::EH_RETURN64: {
478 OutMI.setOpcode(X86::RET);
483 case X86::TAILJMPr:
484 case X86::TAILJMPd:
485 case X86::TAILJMPd64: {
489 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
490 case X86::TAILJMPd:
491 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
504 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
505 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
506 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
507 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
508 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
509 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
510 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
511 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
512 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
518 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
519 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
520 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
521 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
522 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
523 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
524 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
525 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
526 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
527 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
528 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
529 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
530 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
531 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
532 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
533 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
534 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
539 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
540 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
541 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
542 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
543 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
544 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
545 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
546 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
555 case X86::MOV8mr_NOREX:
556 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
557 case X86::MOV8rm_NOREX:
558 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
559 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
560 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
561 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
562 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
564 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
565 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
566 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
567 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
568 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
569 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
570 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
571 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
572 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
573 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
574 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
575 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
576 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
577 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
578 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
579 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
580 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
581 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
582 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
583 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
584 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
585 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
586 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
587 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
588 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
589 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
590 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
591 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
592 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
593 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
594 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
595 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
596 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
597 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
598 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
599 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
601 case X86::MORESTACK_RET:
602 OutMI.setOpcode(X86::RET);
605 case X86::MORESTACK_RET_RESTORE_R10:
606 OutMI.setOpcode(X86::MOV64rr);
607 OutMI.addOperand(MCOperand::CreateReg(X86::R10));
608 OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
610 AsmPrinter.OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
619 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
620 MI.getOpcode() == X86::TLS_base_addr64;
622 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
627 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
631 case X86::TLS_addr32:
632 case X86::TLS_addr64:
635 case X86::TLS_base_addr32:
638 case X86::TLS_base_addr64:
650 LEA.setOpcode(X86::LEA64r);
651 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
652 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
658 LEA.setOpcode(X86::LEA32r);
659 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
660 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
666 LEA.setOpcode(X86::LEA32r);
667 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
670 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
677 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
678 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
679 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX));
689 OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
690 : X86::CALLpcrel32)
707 case X86::Int_MemBarrier:
713 case X86::EH_RETURN:
714 case X86::EH_RETURN64: {
721 case X86::TAILJMPr:
722 case X86::TAILJMPd:
723 case X86::TAILJMPd64:
728 case X86::TLS_addr32:
729 case X86::TLS_addr64:
730 case X86::TLS_base_addr32:
731 case X86::TLS_base_addr64:
734 case X86::MOVPC32r: {
745 OutStreamer.EmitInstruction(MCInstBuilder(X86::CALLpcrel32)
752 OutStreamer.EmitInstruction(MCInstBuilder(X86::POP32r)
757 case X86::ADD32ri: {
783 OutStreamer.EmitInstruction(MCInstBuilder(X86::ADD32ri)
