Lines Matching full:x86
1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
10 // This file describes the X86 Register file, defining the registers themselves,
17 let Namespace = "X86";
23 let Namespace = "X86" in {
41 // variations by target as well. Currently the first entry is for X86-64,
42 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
43 // and debug information on X86-32/Darwin)
52 // High registers. On x86-64, these cannot be used in any instruction
59 // X86-64 only, requires REX.
90 // X86-64 only, requires REX.
114 // X86-64 only, requires REX
126 // 64-bit registers, X86-64 only
179 // X86-64 only
282 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
292 def GR8 : RegisterClass<"X86", [i8], 8,
301 def GR16 : RegisterClass<"X86", [i16], 16,
305 def GR32 : RegisterClass<"X86", [i32], 32,
312 def GR64 : RegisterClass<"X86", [i64], 64,
319 def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>;
322 def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 7)>;
325 def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>;
329 // registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
330 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
333 def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>;
334 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
335 def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>;
336 def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>;
337 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
338 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX)>;
339 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
341 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
345 def GR8_NOREX : RegisterClass<"X86", [i8], 8,
353 def GR16_NOREX : RegisterClass<"X86", [i16], 16,
356 def GR32_NOREX : RegisterClass<"X86", [i32], 32,
359 def GR64_NOREX : RegisterClass<"X86", [i64], 64,
365 def GR32_NOAX : RegisterClass<"X86", [i32], 32, (sub GR32, EAX)>;
368 def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>;
371 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
375 def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32,
379 def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
383 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
386 def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>;
388 def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>;
397 def RFP32 : RegisterClass<"X86
398 def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>;
399 def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>;
404 def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> {
409 def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>;
410 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
412 def VR256 : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
416 def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> {
420 def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> {
