Lines Matching refs:Op2
236 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
249 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
254 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
264 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
342 unsigned Op1, Op2;
343 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
348 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
355 unsigned Op1, Op2;
356 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
361 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
368 unsigned Op1, Op2;
369 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
374 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
381 unsigned Op1, Op2;
382 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
388 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
395 unsigned Op1, Op2;
396 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
401 Inst.addOperand(MCOperand::CreateImm(Op2));
408 unsigned Op1, Op2;
409 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
414 DecodeBitpOperand(Inst, Op2, Address, Decoder);
421 unsigned Op1, Op2;
422 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
428 DecodeBitpOperand(Inst, Op2, Address, Decoder);
506 unsigned Op1, Op2;
508 Op1, Op2);
513 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
520 unsigned Op1, Op2;
522 Op1, Op2);
526 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
534 unsigned Op1, Op2, Op3;
535 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
538 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
547 unsigned Op1, Op2, Op3;
548 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
551 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
560 unsigned Op1, Op2, Op3;
561 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
564 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
573 unsigned Op1, Op2, Op3;
574 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
577 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
586 unsigned Op1, Op2, Op3;
588 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
591 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
600 unsigned Op1, Op2, Op3;
602 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
606 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
615 unsigned Op1, Op2, Op3;
617 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
620 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
629 unsigned Op1, Op2, Op3;
631 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
634 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
643 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
645 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
653 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
677 unsigned Op1, Op2, Op3, Op4, Op5;
679 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
688 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
697 unsigned Op1, Op2, Op3;
700 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
707 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
716 unsigned Op1, Op2, Op3;
719 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
727 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
