Lines Matching refs:KnownZero
55 APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
59 KnownZero, KnownOne, 0);
70 APInt &KnownZero, APInt &KnownOne,
73 KnownZero, KnownOne, Depth);
87 /// to be one in the expression. KnownZero contains all the bits that are known
90 /// the expression. KnownOne and KnownZero always follow the invariant that
91 /// KnownOne & KnownZero == 0. That is, a bit can't be both 1 and 0. Note that
92 /// the bits in KnownOne and KnownZero may only be accurate for those bits set
93 /// in DemandedMask. Note also that the bitwidth of V, DemandedMask, KnownZero
102 APInt &KnownZero, APInt &KnownOne,
113 KnownZero.getBitWidth() == BitWidth &&
115 "Value *V, DemandedMask, KnownZero and KnownOne "
120 KnownZero = ~KnownOne & DemandedMask;
126 KnownZero = DemandedMask;
130 KnownZero.clearAllBits();
146 ComputeMaskedBits(V, KnownZero, KnownOne, Depth);
155 // context, we can at least compute the knownzero/knownone bits, and we can
218 // Compute the KnownZero/KnownOne bits to simplify things downstream.
219 ComputeMaskedBits(I, KnownZero, KnownOne, Depth);
232 ComputeMaskedBits(I, KnownZero, KnownOne, Depth);
264 KnownZero = RHSKnownZero | LHSKnownZero;
299 KnownZero = RHSKnownZero & LHSKnownZero;
373 KnownZero= (RHSKnownZero & LHSKnownZero) | (RHSKnownOne & LHSKnownOne);
394 KnownZero = RHSKnownZero & LHSKnownZero;
399 KnownZero = KnownZero.zext(truncBf);
402 KnownZero, KnownOne, Depth+1))
405 KnownZero = KnownZero.trunc(BitWidth);
407 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
428 KnownZero, KnownOne, Depth+1))
430 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
437 KnownZero = KnownZero.trunc(SrcBitWidth);
440 KnownZero, KnownOne, Depth+1))
443 KnownZero = KnownZero.zext(BitWidth);
445 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
447 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - SrcBitWidth);
464 KnownZero = KnownZero.trunc(SrcBitWidth);
467 KnownZero, KnownOne, Depth+1))
470 KnownZero = KnownZero.zext(BitWidth);
472 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
479 if (KnownZero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) {
549 KnownZero = LHSKnownZero & ~RHSVal & ~CarryBits;
583 ComputeMaskedBits(V, KnownZero, KnownOne, Depth);
589 if ((I0 + 1).isPowerOf2() && (I0 | KnownZero).isAllOnesValue()) {
602 KnownZero, KnownOne);
619 KnownZero, KnownOne, Depth+1))
621 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
622 KnownZero <<= ShiftAmt;
626 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
643 KnownZero, KnownOne, Depth+1))
645 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
646 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
651 KnownZero |= HighBits; // high bits known zero.
688 KnownZero, KnownOne, Depth+1))
690 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
693 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
703 if (BitWidth <= ShiftAmt || KnownZero[BitWidth-ShiftAmt-1] ||
733 KnownZero = LHSKnownZero & LowBits;
739 KnownZero |= ~LowBits;
746 assert(!(KnownZero & KnownOne) && "Bits known to be one AND zero?");
752 if (DemandedMask.isNegative() && KnownZero.isNonNegative()) {
757 KnownZero |= LHSKnownZero;
772 KnownZero = APInt::getHighBitsSet(BitWidth, Leaders) & DemandedMask;
813 KnownZero = APInt::getHighBitsSet(64, 32);
817 ComputeMaskedBits(V, KnownZero, KnownOne, Depth);
823 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
846 Instruction *Shl, APInt DemandedMask, APInt &KnownZero, APInt &KnownOne) {
852 KnownZero = APInt::getBitsSet(KnownZero.getBitWidth(), 0, ShlAmt-1);
853 KnownZero &= DemandedMask;
