Lines Matching refs:Idx
61 CodeGenSchedRW(unsigned Idx, Record *Def)
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
75 CodeGenSchedRW(unsigned Idx, bool Read, const IdxVec &Seq,
77 : Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false),
173 // ItinDefList orders this processor's InstrItinData records by SchedClass idx.
199 CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef,
201 Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
284 const CodeGenSchedRW &getSchedWrite(unsigned Idx) const {
285 assert(Idx < SchedWrites.size() && "bad SchedWrite index");
286 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
287 return SchedWrites[Idx];
290 const CodeGenSchedRW &getSchedRead(unsigned Idx) const {
291 assert(Idx < SchedReads.size() && "bad SchedRead index");
292 assert(SchedReads[Idx].isValid() && "invalid SchedRead");
293 return SchedReads[Idx];
296 const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
297 return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
301 unsigned Idx = getSchedRWIdx(Def, IsRead);
303 IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
315 CodeGenSchedClass &getSchedClass(unsigned Idx) {
316 assert(Idx < SchedClasses.size() && "bad SchedClass index");
317 return SchedClasses[Idx];
319 const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
320 assert(Idx < SchedClasses.size() && "bad SchedClass index");
321 return SchedClasses[Idx];
