Lines Matching refs:CTR
2 {0x00, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PMNC_SW_INCR",
4 {0x01, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "IFETCH_MISS",
6 {0x02, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "ITLB_MISS",
8 {0x03, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "DCACHE_REFILL",
10 {0x04, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "DCACHE_ACCESS",
12 {0x05, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "DTLB_REFILL",
14 {0x06, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "DREAD",
16 {0x07, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "DWRITE",
18 {0x08, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "INSTR_EXECUTED",
20 {0x09, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "EXC_TAKEN",
22 {0x0A, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "EXC_EXECUTED",
24 {0x0B, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "CID_WRITE",
26 {0x0C, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PC_WRITE",
28 {0x0D, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PC_IMM_BRANCH",
30 {0x0E, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PC_PROC_RETURN",
32 {0x0F, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "UNALIGNED_ACCESS",
34 {0x10, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PC_BRANCH_MIS_PRED",
36 {0x12, CTR(1) | CTR(2) | CTR(3) | CTR(4) | CTR(5) | CTR(6), 0, "PC_BRANCH_MIS_USED",
38 {0xFF, CTR(0), 0, "CPU_CYCLES",
41 {0x40, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "WRITE_BUFFER_FULL",
43 {0x41, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_STORE_MERGED",
45 {0x42, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_STORE_BUFF",
47 {0x43, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_ACCESS",
49 {0x44, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_CACH_MISS",
51 {0x45, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "AXI_READ_CYCLES",
53 {0x46, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "AXI_WRITE_CYCLES",
55 {0x47, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "MEMORY_REPLAY",
57 {0x48, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "UNALIGNED_ACCESS_REPLAY",
59 {0x49, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_DATA_MISS",
61 {0x4A, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_INST_MISS",
63 {0x4B, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_DATA_COLORING",
65 {0x4C, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_NEON_DATA",
67 {0x4D, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_NEON_CACH_DATA",
69 {0x4E, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_NEON",
71 {0x4F, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L2_NEON_HIT",
73 {0x50, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "L1_INST",
75 {0x51, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PC_RETURN_MIS_PRED",
77 {0x52, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PC_BRANCH_FAILED",
79 {0x53, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PC_BRANCH_TAKEN",
81 {0x54, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PC_BRANCH_EXECUTED",
83 {0x55, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "OP_EXECUTED",
85 {0x56, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "CYCLES_INST_STALL",
87 {0x57, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "CYCLES_INST",
89 {0x58, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "CYCLES_NEON_DATA_STALL",
91 {0x59, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "CYCLES_NEON_INST_STALL",
93 {0x5A, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "NEON_CYCLES",
95 {0x70, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PMU0_EVENTS",
97 {0x71, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PMU1_EVENTS",
99 {0x72, CTR(1) | CTR(2) | CTR(3) | CTR(4), 0, "PMU_EVENTS",
