Lines Matching refs:env
45 #undef env
46 #define env cpu_single_env
54 int qemu_cpu_has_work(CPUState *env)
56 return cpu_has_work(env);
61 env->current_tb = NULL;
62 longjmp(env->jmp_env, 1);
78 env = env1;
96 env->exception_index = -1;
97 longjmp(env->jmp_env, 1);
112 tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
114 env->current_tb = tb;
117 env->current_tb = NULL;
122 cpu_pc_from_tb(env, tb);
139 phys_pc = get_phys_addr_code(env, pc);
156 phys_page2 = get_phys_addr_code(env, virt_page2);
167 tb = tb_gen_code(env, pc, cs_base, flags, 0);
177 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
190 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
191 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
209 static void cpu_handle_debug_exception(CPUState *env)
213 if (!env->watchpoint_hit) {
214 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
219 debug_excp_handler(env);
233 int need_handle_intr_request(CPUState *env)
236 if (!hax_enabled() || hax_vcpu_emulation_mode(env))
237 return env->interrupt_request;
240 return env->interrupt_request;
262 /* the access to env below is actually saving the global register's
265 QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env));
266 saved_env_reg = (host_reg_t) env;
268 env = env1;
271 env->exit_request = 1;
277 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
278 DF = 1 - (2 * ((env->eflags >> 10) & 1));
280 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
284 env->cc_op = CC_OP_FLAGS;
285 env->cc_dest = env->sr & 0xf;
286 env->cc_x = (env->sr >> 4) & 1;
301 env->exception_index = -1;
305 if (setjmp(env->jmp_env) == 0) {
307 #undef env
308 env = cpu_single_env;
309 #define env cpu_single_env
312 if (env->exception_index >= 0) {
313 if (env->exception_index >= EXCP_INTERRUPT) {
315 ret = env->exception_index;
317 cpu_handle_debug_exception(env);
326 do_interrupt_user(env->exception_index,
327 env->exception_is_int,
328 env->error_code,
329 env->exception_next_eip);
331 env->old_exception = -1;
333 ret = env->exception_index;
340 do_interrupt(env->exception_index,
341 env->exception_is_int,
342 env->error_code,
343 env->exception_next_eip, 0);
345 env->old_exception = -1;
347 do_interrupt(env);
349 do_interrupt(env);
351 do_interrupt(env);
353 do_interrupt(env);
355 do_interrupt(env);
357 do_interrupt(env);
359 do_interrupt(env);
361 do_interrupt(env);
363 do_interrupt(env);
365 do_interrupt(env);
369 do_interrupt(env);
371 env->exception_index = -1;
377 if (hax_enabled() && !hax_vcpu_exec(env))
378 longjmp(env->jmp_env, 1);
382 kvm_cpu_exec(env);
383 longjmp(env->jmp_env, 1);
388 interrupt_request = env->interrupt_request;
389 if (unlikely(need_handle_intr_request(env))) {
390 if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
395 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
396 env->exception_index = EXCP_DEBUG;
403 env->interrupt_request &= ~CPU_INTERRUPT_HALT;
404 env->halted = 1;
405 env->exception_index = EXCP_HLT;
412 do_cpu_init(env);
413 env->exception_index = EXCP_HALTED;
416 do_cpu_sipi(env);
417 } else if (env->hflags2 & HF2_GIF_MASK) {
419 !(env->hflags & HF_SMM_MASK)) {
421 env->interrupt_request &= ~CPU_INTERRUPT_SMI;
425 !(env->hflags2 & HF2_NMI_MASK)) {
426 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
427 env->hflags2 |= HF2_NMI_MASK;
431 env->interrupt_request &= ~CPU_INTERRUPT_MCE;
435 (((env->hflags2 & HF2_VINTR_MASK) &&
436 (env->hflags2 & HF2_HIF_MASK)) ||
437 (!(env->hflags2 & HF2_VINTR_MASK) &&
438 (env->eflags & IF_MASK &&
439 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
442 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
443 intno = cpu_get_pic_interrupt(env);
446 #undef env
447 env = cpu_single_env;
448 #define env cpu_single_env
456 (env->eflags & IF_MASK) &&
457 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
461 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
464 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
472 cpu_reset(env);
476 ppc_hw_interrupt(env);
477 if (env->pending_interrupts == 0)
478 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
483 && (env->ie & IE_IE)) {
484 env->exception_index = EXCP_IRQ;
485 do_interrupt(env);
490 && (env->sregs[SR_MSR] & MSR_IE)
491 && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
492 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
493 env->exception_index = EXCP_IRQ;
494 do_interrupt(env);
499 cpu_mips_hw_interrupts_pending(env)) {
501 env->exception_index = EXCP_EXT_INTERRUPT;
502 env->error_code = 0;
503 do_interrupt(env);
508 if (cpu_interrupts_enabled(env) &&
509 env->interrupt_index > 0) {
510 int pil = env->interrupt_index & 0xf;
511 int type = env->interrupt_index & 0xf0;
514 cpu_pil_allowed(env, pil)) ||
516 env->exception_index = env->interrupt_index;
517 do_interrupt(env);
524 && !(env->uncached_cpsr & CPSR_F)) {
525 env->exception_index = EXCP_FIQ;
526 do_interrupt(env);
539 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
540 || !(env->uncached_cpsr & CPSR_I))) {
541 env->exception_index = EXCP_IRQ;
542 do_interrupt(env);
547 && !(env->uncached_asr & ASR_I)) {
548 do_interrupt(env);
553 do_interrupt(env);
558 do_interrupt(env);
563 && (env->pregs[PR_CCS] & I_FLAG)
564 && !env->locked_irq) {
565 env->exception_index = EXCP_IRQ;
566 do_interrupt(env);
570 && (env->pregs[PR_CCS] & M_FLAG)) {
571 env->exception_index = EXCP_NMI;
572 do_interrupt(env);
577 && ((env->sr & SR_I) >> SR_I_SHIFT)
578 < env->pending_level) {
584 env->exception_index = env->pending_vector;
590 (env->psw.mask & PSW_MASK_EXT)) {
591 do_interrupt(env);
597 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
598 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
604 if (unlikely(env->exit_request)) {
605 env->exit_request = 0;
606 env->exception_index = EXCP_INTERRUPT;
613 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
614 log_cpu_state(env, X86_DUMP_CCOP);
615 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
617 cpu_m68k_flush_flags(env, env->cc_op);
618 env->cc_op = CC_OP_FLAGS;
619 env->sr = (env->sr & 0xffe0)
620 | env->cc_dest | (env->cc_x << 4);
621 log_cpu_state(env, 0);
623 log_cpu_state(env, 0);
653 infinite loop and becomes env->current_tb. Avoid
655 env->current_tb = tb;
657 if (likely(!env->exit_request)) {
661 #undef env
662 env = cpu_single_env;
663 #define env cpu_single_env
671 cpu_pc_from_tb(env, tb);
672 insns_left = env->icount_decr.u32;
673 if (env->icount_extra && insns_left >= 0) {
675 env->icount_extra += insns_left;
676 if (env->icount_extra > 0xffff) {
679 insns_left = env->icount_extra;
681 env->icount_extra -= insns_left;
682 env->icount_decr.u16.low = insns_left;
688 env->exception_index = EXCP_INTERRUPT;
694 env->current_tb = NULL;
696 if (hax_enabled() && hax_stop_emulation(env))
708 env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
716 cpu_m68k_flush_flags(env, env->cc_op);
717 env->cc_op = CC_OP_FLAGS;
718 env->sr = (env->sr & 0xffe0)
719 | env->cc_dest | (env->cc_x << 4);
733 env = (void *) saved_env_reg;
748 phys_addr = get_phys_addr_code(env, start);
759 saved_env = env;
760 env = s;
761 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
763 cpu_x86_load_seg_cache(env, seg_reg, selector,
768 env = saved_env;
775 saved_env = env;
776 env = s;
780 env = saved_env;
787 saved_env = env;
788 env = s;
792 env = saved_env;
800 #define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
817 env = cpu_single_env; /* XXX: find a correct solution for multithread */
828 ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
838 cpu_restore_state(tb, env, pc);
