Lines Matching refs:env
27 CPUState *env = opaque;
33 cpu_synchronize_state(env, 0);
36 qemu_put_betls(f, &env->regs[i]);
37 qemu_put_betls(f, &env->eip);
38 qemu_put_betls(f, &env->eflags);
39 hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
43 fpuc = env->fpuc;
44 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
47 fptag |= ((!env->fptags[i]) << i);
68 cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
77 qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
82 cpu_put_seg(f, &env->segs[i]);
83 cpu_put_seg(f, &env->ldt);
84 cpu_put_seg(f, &env->tr);
85 cpu_put_seg(f, &env->gdt);
86 cpu_put_seg(f, &env->idt);
88 qemu_put_be32s(f, &env->sysenter_cs);
89 qemu_put_betls(f, &env->sysenter_esp);
90 qemu_put_betls(f, &env->sysenter_eip);
92 qemu_put_betls(f, &env->cr[0]);
93 qemu_put_betls(f, &env->cr[2]);
94 qemu_put_betls(f, &env->cr[3]);
95 qemu_put_betls(f, &env->cr[4]);
98 qemu_put_betls(f, &env->dr[i]);
101 a20_mask = (int32_t) env->a20_mask;
105 qemu_put_be32s(f, &env->mxcsr);
107 qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
108 qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
112 qemu_put_be64s(f, &env->efer);
113 qemu_put_be64s(f, &env->star);
114 qemu_put_be64s(f, &env->lstar);
115 qemu_put_be64s(f, &env->cstar);
116 qemu_put_be64s(f, &env->fmask);
117 qemu_put_be64s(f, &env->kernelgsbase);
119 qemu_put_be32s(f, &env->smbase);
121 qemu_put_be64s(f, &env->pat);
122 qemu_put_be32s(f, &env->hflags2);
124 qemu_put_be64s(f, &env->vm_hsave);
125 qemu_put_be64s(f, &env->vm_vmcb);
126 qemu_put_be64s(f, &env->tsc_offset);
127 qemu_put_be64s(f, &env->intercept);
128 qemu_put_be16s(f, &env->intercept_cr_read);
129 qemu_put_be16s(f, &env->intercept_cr_write);
130 qemu_put_be16s(f, &env->intercept_dr_read);
131 qemu_put_be16s(f, &env->intercept_dr_write);
132 qemu_put_be32s(f, &env->intercept_exceptions);
133 qemu_put_8s(f, &env->v_tpr);
137 qemu_put_be64s(f, &env->mtrr_fixed[i]);
138 qemu_put_be64s(f, &env->mtrr_deftype);
140 qemu_put_be64s(f, &env->mtrr_var[i].base);
141 qemu_put_be64s(f, &env->mtrr_var[i].mask);
144 for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
145 qemu_put_be64s(f, &env->interrupt_bitmap[i]);
147 qemu_put_be64s(f, &env->tsc);
148 qemu_put_be32s(f, &env->mp_state);
151 qemu_put_be64s(f, &env->mcg_cap);
152 if (env->mcg_cap) {
153 qemu_put_be64s(f, &env->mcg_status);
154 qemu_put_be64s(f, &env->mcg_ctl);
155 for (i = 0; i < (env->mcg_cap & 0xff); i++) {
156 qemu_put_be64s(f, &env->mce_banks[4*i]);
157 qemu_put_be64s(f, &env->mce_banks[4*i + 1]);
158 qemu_put_be64s(f, &env->mce_banks[4*i + 2]);
159 qemu_put_be64s(f, &env->mce_banks[4*i + 3]);
190 CPUState *env = opaque;
199 qemu_get_betls(f, &env->regs[i]);
200 qemu_get_betls(f, &env->eip);
201 qemu_get_betls(f, &env->eflags);
222 env->fpregs[i].d = cpu_set_fp80(mant, exp);
226 env->fpregs[i].mmx.MMX_Q(0) = mant;
228 env->fpregs[i].d = cpu_set_fp80(mant, exp);
237 p = (void *)&env->fpregs[i];
246 env->fpregs[i].mmx.MMX_Q(0) = mant;
254 env->fpuc = fpuc;
256 env->fpstt = (fpus >> 11) & 7;
257 env->fpus = fpus & ~0x3800;
260 env->fptags[i] = (fptag >> i) & 1;
264 cpu_get_seg(f, &env->segs[i]);
265 cpu_get_seg(f, &env->ldt);
266 cpu_get_seg(f, &env->tr);
267 cpu_get_seg(f, &env->gdt);
268 cpu_get_seg(f, &env->idt);
270 qemu_get_be32s(f, &env->sysenter_cs);
272 qemu_get_betls(f, &env->sysenter_esp);
273 qemu_get_betls(f, &env->sysenter_eip);
275 env->sysenter_esp = qemu_get_be32(f);
276 env->sysenter_eip = qemu_get_be32(f);
279 qemu_get_betls(f, &env->cr[0]);
280 qemu_get_betls(f, &env->cr[2]);
281 qemu_get_betls(f, &env->cr[3]);
282 qemu_get_betls(f, &env->cr[4]);
285 qemu_get_betls(f, &env->dr[i]);
286 cpu_breakpoint_remove_all(env, BP_CPU);
287 cpu_watchpoint_remove_all(env, BP_CPU);
289 hw_breakpoint_insert(env, i);
293 env->a20_mask = a20_mask;
295 qemu_get_be32s(f, &env->mxcsr);
297 qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
298 qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
302 qemu_get_be64s(f, &env->efer);
303 qemu_get_be64s(f, &env->star);
304 qemu_get_be64s(f, &env->lstar);
305 qemu_get_be64s(f, &env->cstar);
306 qemu_get_be64s(f, &env->fmask);
307 qemu_get_be64s(f, &env->kernelgsbase);
310 qemu_get_be32s(f, &env->smbase);
313 qemu_get_be64s(f, &env->pat);
314 qemu_get_be32s(f, &env->hflags2);
316 qemu_get_be32s(f, &env->halted);
318 qemu_get_be64s(f, &env->vm_hsave);
319 qemu_get_be64s(f, &env->vm_vmcb);
320 qemu_get_be64s(f, &env->tsc_offset);
321 qemu_get_be64s(f, &env->intercept);
322 qemu_get_be16s(f, &env->intercept_cr_read);
323 qemu_get_be16s(f, &env->intercept_cr_write);
324 qemu_get_be16s(f, &env->intercept_dr_read);
325 qemu_get_be16s(f, &env->intercept_dr_write);
326 qemu_get_be32s(f, &env->intercept_exceptions);
327 qemu_get_8s(f, &env->v_tpr);
333 qemu_get_be64s(f, &env->mtrr_fixed[i]);
334 qemu_get_be64s(f, &env->mtrr_deftype);
336 qemu_get_be64s(f, &env->mtrr_var[i].base);
337 qemu_get_be64s(f, &env->mtrr_var[i].mask);
341 for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
342 qemu_get_be64s(f, &env->interrupt_bitmap[i]);
344 qemu_get_be64s(f, &env->tsc);
345 qemu_get_be32s(f, &env->mp_state);
349 qemu_get_be64s(f, &env->mcg_cap);
350 if (env->mcg_cap) {
351 qemu_get_be64s(f, &env->mcg_status);
352 qemu_get_be64s(f, &env->mcg_ctl);
353 for (i = 0; i < (env->mcg_cap & 0xff); i++) {
354 qemu_get_be64s(f, &env->mce_banks[4*i]);
355 qemu_get_be64s(f, &env->mce_banks[4*i + 1]);
356 qemu_get_be64s(f, &env->mce_banks[4*i + 2]);
357 qemu_get_be64s(f, &env->mce_banks[4*i + 3]);
365 env->hflags = hflags;
366 tlb_flush(env, 1);
367 cpu_synchronize_state(env, 1);
