Lines Matching refs:env
34 env->exception_index = exception;
35 env->error_code = error_code;
46 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
47 !(env->CP0_Status & (1 << CP0St_ERL)) &&
48 !(env->hflags & MIPS_HFLAG_DM) &&
49 (env->CP0_Status & (1 << CP0St_IE)) &&
50 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
51 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
64 cpu_restore_state (tb, env, pc);
146 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
151 env->active_tc.LO[0] = (int32_t)HILO;
152 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
157 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
158 arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
163 arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
164 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
269 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
274 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
284 lladdr = cpu_mips_translate_address(env, address, rw);
296 env->lladdr = do_translate_address(arg, 0); \
297 env->llval = do_##insn(arg, mem_idx); \
298 return env->llval; \
312 env->CP0_BadVAddr = arg2; \
315 if (do_translate_address(arg2, 1) == env->lladdr) { \
317 if (tmp == env->llval) { \
572 return env->mvp->CP0_MVPControl;
577 return env->mvp->CP0_MVPConf0;
582 return env->mvp->CP0_MVPConf1;
587 return (int32_t)cpu_mips_get_random(env);
592 return env->active_tc.CP0_TCStatus;
597 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
599 if (other_tc == env->current_tc)
600 return env->active_tc.CP0_TCStatus;
602 return env->tcs[other_tc].CP0_TCStatus;
607 return env->active_tc.CP0_TCBind;
612 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
614 if (other_tc == env->current_tc)
615 return env->active_tc.CP0_TCBind;
617 return env->tcs[other_tc].CP0_TCBind;
622 return env->active_tc.PC;
627 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
629 if (other_tc == env->current_tc)
630 return env->active_tc.PC;
632 return env->tcs[other_tc].PC;
637 return env->active_tc.CP0_TCHalt;
642 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
644 if (other_tc == env->current_tc)
645 return env->active_tc.CP0_TCHalt;
647 return env->tcs[other_tc].CP0_TCHalt;
652 return env->active_tc.CP0_TCContext;
657 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
659 if (other_tc == env->current_tc)
660 return env->active_tc.CP0_TCContext;
662 return env->tcs[other_tc].CP0_TCContext;
667 return env->active_tc.CP0_TCSchedule;
672 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
674 if (other_tc == env->current_tc)
675 return env->active_tc.CP0_TCSchedule;
677 return env->tcs[other_tc].CP0_TCSchedule;
682 return env->active_tc.CP0_TCScheFBack;
687 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
689 if (other_tc == env->current_tc)
690 return env->active_tc.CP0_TCScheFBack;
692 return env->tcs[other_tc].CP0_TCScheFBack;
697 return (int32_t)cpu_mips_get_count(env);
702 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
705 if (other_tc == env->current_tc)
706 tcstatus = env->active_tc.CP0_TCStatus;
708 tcstatus = env->tcs[other_tc].CP0_TCStatus;
710 return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
715 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
719 if (other_tc == env->current_tc)
720 tcstatus = env->active_tc.CP0_TCStatus;
722 tcstatus = env->tcs[other_tc].CP0_TCStatus;
724 t0 = env->CP0_Status & ~0xf1000018;
734 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
739 return (int32_t)env->CP0_WatchLo[sel];
744 return env->CP0_WatchHi[sel];
749 target_ulong t0 = env->CP0_Debug;
750 if (env->hflags & MIPS_HFLAG_DM)
758 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
761 if (other_tc == env->current_tc)
762 tcstatus = env->active_tc.CP0_Debug_tcstatus;
764 tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;
767 return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
774 return env->active_tc.PC;
779 return env->active_tc.CP0_TCHalt;
784 return env->active_tc.CP0_TCContext;
789 return env->active_tc.CP0_TCSchedule;
794 return env->active_tc.CP0_TCScheFBack;
799 return env->lladdr >> env->CP0_LLAddr_shift;
804 return env->CP0_WatchLo[sel];
811 unsigned int tmp = env->tlb->nb_tlb;
817 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
825 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
828 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
830 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
834 env->mvp->CP0_MVPControl = newval;
844 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
851 env->CP0_VPEControl = newval;
859 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
860 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
864 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
868 env->CP0_VPEConf0 = newval;
876 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
879 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
886 env->CP0_VPEConf1 = newval;
892 env->CP0_YQMask = 0x00000000;
897 env->CP0_VPEOpt = arg1 & 0x0000ffff;
904 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
909 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
912 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
916 env->active_tc.CP0_TCStatus = newval;
921 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
925 if (other_tc == env->current_tc)
926 env->active_tc.CP0_TCStatus = arg1;
928 env->tcs[other_tc].CP0_TCStatus = arg1;
936 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
938 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
939 env->active_tc.CP0_TCBind = newval;
944 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
948 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
950 if (other_tc == env->current_tc) {
951 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
952 env->active_tc.CP0_TCBind = newval;
954 newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
955 env->tcs[other_tc].CP0_TCBind = newval;
961 env->active_tc.PC = arg1;
962 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
963 env->lladdr = 0ULL;
969 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
971 if (other_tc == env->current_tc) {
972 env->active_tc.PC = arg1;
973 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
974 env->lladdr = 0ULL;
977 env->tcs[other_tc].PC = arg1;
978 env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
979 env->lladdr = 0ULL;
986 env->active_tc.CP0_TCHalt = arg1 & 0x1;
993 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
997 if (other_tc == env->current_tc)
998 env->active_tc.CP0_TCHalt = arg1;
1000 env->tcs[other_tc].CP0_TCHalt = arg1;
1005 env->active_tc.CP0_TCContext = arg1;
1010 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1012 if (other_tc == env->current_tc)
1013 env->active_tc.CP0_TCContext = arg1;
1015 env->tcs[other_tc].CP0_TCContext = arg1;
1020 env->active_tc.CP0_TCSchedule = arg1;
1025 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1027 if (other_tc == env->current_tc)
1028 env->active_tc.CP0_TCSchedule = arg1;
1030 env->tcs[other_tc].CP0_TCSchedule = arg1;
1035 env->active_tc.CP0_TCScheFBack = arg1;
1040 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1042 if (other_tc == env->current_tc)
1043 env->active_tc.CP0_TCScheFBack = arg1;
1045 env->tcs[other_tc].CP0_TCScheFBack = arg1;
1052 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1057 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1063 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1071 env->CP0_PageGrain = 0;
1076 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1081 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1086 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1091 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1096 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1101 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1106 env->CP0_HWREna = arg1 & 0x0000000F;
1111 cpu_mips_store_count(env, arg1);
1121 val &= env->SEGMask;
1123 old = env->CP0_EntryHi;
1124 env->CP0_EntryHi = val;
1125 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1126 uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1127 env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
1131 cpu_mips_tlb_flush(env, 1);
1136 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1139 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
1140 if (other_tc == env->current_tc) {
1141 tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1142 env->active_tc.CP0_TCStatus = tcstatus;
1144 tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
1145 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1151 cpu_mips_store_compare(env, arg1);
1157 uint32_t mask = env->CP0_Status_rw_bitmask;
1160 old = env->CP0_Status;
1161 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1162 compute_hflags(env);
1165 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1166 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1167 env->CP0_Cause);
1168 switch (env->hflags & MIPS_HFLAG_KSU) {
1172 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1175 cpu_mips_update_irq(env);
1180 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1181 int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
1183 env->CP0_Status = arg1 & ~0xf1000018;
1187 if (other_tc == env->current_tc)
1188 env->active_tc.CP0_TCStatus = tcstatus;
1190 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1196 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
1202 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1208 uint32_t old = env->CP0_Cause;
1210 if (env->insn_flags & ISA_MIPS32R2)
1213 env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
1215 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1216 if (env->CP0_Cause & (1 << CP0Ca_DC))
1217 cpu_mips_stop_count(env);
1219 cpu_mips_start_count(env);
1225 cpu_mips_update_irq(env);
1233 env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
1238 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1244 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1249 target_long mask = env->CP0_LLAddr_rw_bitmask;
1250 arg1 = arg1 << env->CP0_LLAddr_shift;
1251 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1258 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1263 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1264 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1269 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1270 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1275 env->CP0_Framemask = arg1; /* XXX */
1280 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1282 env->hflags |= MIPS_HFLAG_DM;
1284 env->hflags &= ~MIPS_HFLAG_DM;
1289 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1293 if (other_tc == env->current_tc)
1294 env->active_tc.CP0_Debug_tcstatus = val;
1296 env->tcs[other_tc].CP0_Debug_tcstatus = val;
1297 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1303 env->CP0_Performance0 = arg1 & 0x000007ff;
1308 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1313 env->CP0_DataLo = arg1; /* XXX */
1318 env->CP0_TagHi = arg1; /* XXX */
1323 env->CP0_DataHi = arg1; /* XXX */
1329 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1331 if (other_tc == env->current_tc)
1332 return env->active_tc.gpr[sel];
1334 return env->tcs[other_tc].gpr[sel];
1339 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1341 if (other_tc == env->current_tc)
1342 return env->active_tc.LO[sel];
1344 return env->tcs[other_tc].LO[sel];
1349 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1351 if (other_tc == env->current_tc)
1352 return env->active_tc.HI[sel];
1354 return env->tcs[other_tc].HI[sel];
1359 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1361 if (other_tc == env->current_tc)
1362 return env->active_tc.ACX[sel];
1364 return env->tcs[other_tc].ACX[sel];
1369 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1371 if (other_tc == env->current_tc)
1372 return env->active_tc.DSPControl;
1374 return env->tcs[other_tc].DSPControl;
1379 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1381 if (other_tc == env->current_tc)
1382 env->active_tc.gpr[sel] = arg1;
1384 env->tcs[other_tc].gpr[sel] = arg1;
1389 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1391 if (other_tc == env->current_tc)
1392 env->active_tc.LO[sel] = arg1;
1394 env->tcs[other_tc].LO[sel] = arg1;
1399 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1401 if (other_tc == env->current_tc)
1402 env->active_tc.HI[sel] = arg1;
1404 env->tcs[other_tc].HI[sel] = arg1;
1409 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1411 if (other_tc == env->current_tc)
1412 env->active_tc.ACX[sel] = arg1;
1414 env->tcs[other_tc].ACX[sel] = arg1;
1419 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1421 if (other_tc == env->current_tc)
1422 env->active_tc.DSPControl = arg1;
1424 env->tcs[other_tc].DSPControl = arg1;
1477 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1478 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1479 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1480 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1486 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1493 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1494 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1497 return env->CP0_YQMask;
1501 static void inline r4k_invalidate_tlb_shadow (CPUState *env, int idx)
1504 uint8_t ASID = env->CP0_EntryHi & 0xFF;
1506 tlb = &env->tlb->mmu.r4k.tlb[idx];
1514 static void inline r4k_invalidate_tlb (CPUState *env, int idx)
1519 uint8_t ASID = env->CP0_EntryHi & 0xFF;
1522 tlb = &env->tlb->mmu.r4k.tlb[idx];
1534 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1540 tlb_flush_page (env, addr);
1547 if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
1553 tlb_flush_page (env, addr);
1560 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1563 tlb_flush (env, flush_global);
1571 tlb = &env->tlb->mmu.r4k.tlb[idx];
1572 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1574 tlb->VPN &= env->SEGMask;
1576 tlb->ASID = env->CP0_EntryHi & 0xFF;
1577 tlb->PageMask = env->CP0_PageMask;
1578 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1579 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1580 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1581 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1582 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1583 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1584 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1585 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1586 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1593 /* Save current 'env' value */
1594 saved_env = env;
1595 env = target_env;
1598 int r = cpu_mips_get_random(env);
1599 r4k_invalidate_tlb_shadow(env, r);
1602 /* Restore 'env' value */
1603 env = saved_env;
1616 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
1618 tag = env->CP0_EntryHi & ~mask;
1622 if (tlb->ASID == (env->CP0_EntryHi & 0xFF))
1624 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1625 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1626 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1627 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1628 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1629 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1630 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1631 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1637 cpu_mips_tlb_flush (env, 1);
1639 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb);
1640 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
1645 int r = cpu_mips_get_random(env);
1647 r4k_invalidate_tlb_shadow(env, r);
1662 ASID = env->CP0_EntryHi & 0xFF;
1663 for (i = 0; i < env->tlb->nb_tlb; i++) {
1664 tlb = &env->tlb->mmu.r4k.tlb[i];
1667 tag = env->CP0_EntryHi & ~mask;
1672 env->CP0_Index = i;
1676 if (i == env->tlb->nb_tlb) {
1678 int index = ((env->CP0_EntryHi>>5)&0x1ff00) | ASID;
1679 index |= (env->CP0_EntryHi>>13)&0x20000;
1680 env->CP0_Index |= 0x80000000;
1689 ASID = env->CP0_EntryHi & 0xFF;
1690 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
1694 cpu_mips_tlb_flush (env, 1);
1697 cpu_mips_tlb_flush (env, 1);
1699 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1700 env->CP0_PageMask = tlb->PageMask;
1701 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1703 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1709 env->tlb->helper_tlbwi();
1714 env->tlb->helper_tlbwr();
1719 env->tlb->helper_tlbp();
1724 env->tlb->helper_tlbr();
1730 target_ulong t0 = env->CP0_Status;
1732 env->CP0_Status = t0 & ~(1 << CP0St_IE);
1733 cpu_mips_update_irq(env);
1740 target_ulong t0 = env->CP0_Status;
1742 env->CP0_Status = t0 | (1 << CP0St_IE);
1743 cpu_mips_update_irq(env);
1752 env->active_tc.PC, env->CP0_EPC);
1753 if (env->CP0_Status & (1 << CP0St_ERL))
1754 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1755 if (env->hflags & MIPS_HFLAG_DM)
1756 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1765 env->active_tc.PC, env->CP0_EPC);
1766 if (env->CP0_Status & (1 << CP0St_ERL))
1767 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1768 if (env->hflags & MIPS_HFLAG_DM)
1769 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1770 switch (env->hflags & MIPS_HFLAG_KSU) {
1774 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1782 if (env->CP0_Status & (1 << CP0St_ERL)) {
1783 env->active_tc.PC = env->CP0_ErrorEPC;
1784 env->CP0_Status &= ~(1 << CP0St_ERL);
1786 env->active_tc.PC = env->CP0_EPC;
1787 env->CP0_Status &= ~(1 << CP0St_EXL);
1789 compute_hflags(env);
1791 env->lladdr = 1;
1797 env->active_tc.PC = env->CP0_DEPC;
1798 env->hflags &= MIPS_HFLAG_DM;
1799 compute_hflags(env);
1801 env->lladdr = 1;
1807 if ((env
1808 (env->CP0_HWREna & (1 << 0)))
1809 return env->CP0_EBase & 0x3ff;
1818 if ((env->hflags & MIPS_HFLAG_CP0) ||
1819 (env->CP0_HWREna & (1 << 1)))
1820 return env->SYNCI_Step;
1829 if ((env->hflags & MIPS_HFLAG_CP0) ||
1830 (env->CP0_HWREna & (1 << 2)))
1831 return env->CP0_Count;
1840 if ((env->hflags & MIPS_HFLAG_CP0) ||
1841 (env->CP0_HWREna & (1 << 3)))
1842 return env->CCRes;
1854 if (env->active_tc.gpr[4] == 0)
1855 env->active_tc.gpr[2] = -1;
1858 env->active_tc.gpr[2] = -1;
1862 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
1868 unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
1877 env->halted = 1;
1902 env->CP0_BadVAddr = addr;
1914 /* XXX: hack to restore env in all cases, even if not called from
1916 saved_env = env;
1917 env = cpu_single_env;
1918 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
1927 cpu_restore_state(tb, env, pc);
1930 helper_raise_exception_err(env->exception_index, env->error_code);
1932 env = saved_env;
1956 tlb_addr = env->tlb_table[is_user][index].addr_read;
1958 physaddr = addr + env->tlb_table[is_user][index].addend;
1980 saved_env = env;
1981 env = cpu_single_env;
1984 if (__builtin_expect(env->tlb_table[is_user][index].addr_read !=
1988 physaddr = addr + env->tlb_table[is_user][index].addend;
1990 env = saved_env;
2039 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
2042 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
2050 arg1 = (int32_t)env->active_fpu.fcr0;
2053 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2056 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2059 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2062 arg1 = (int32_t)env->active_fpu.fcr31;
2075 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2081 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2086 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2092 env->active_fpu.fcr31 = arg1;
2101 set_float_exception_flags(0, &env->active_fpu.fp_status);
2102 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2126 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2128 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2129 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
2132 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2143 return float64_sqrt(fdt0, &env->active_fpu.fp_status);
2148 return float32_sqrt(fst0, &env->active_fpu.fp_status);
2155 set_float_exception_flags(0, &env->active_fpu.fp_status);
2156 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2165 set_float_exception_flags(0, &env->active_fpu.fp_status);
2166 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2175 set_float_exception_flags(0, &env->active_fpu.fp_status);
2176 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2185 set_float_exception_flags(0, &env->active_fpu.fp_status);
2186 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2188 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2197 set_float_exception_flags(0, &env->active_fpu.fp_status);
2198 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2200 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2210 set_float_exception_flags(0, &env->active_fpu.fp_status);
2211 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2212 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2222 set_float_exception_flags(0, &env->active_fpu.fp_status);
2223 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2224 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2226 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
2237 set_float_exception_flags(0, &env->active_fpu.fp_status);
2238 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2247 set_float_exception_flags(0, &env->active_fpu.fp_status);
2248 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2257 set_float_exception_flags(0, &env->active_fpu.fp_status);
2258 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2267 set_float_exception_flags(0, &env->active_fpu.fp_status);
2277 set_float_exception_flags(0, &env->active_fpu.fp_status);
2287 set_float_exception_flags(0, &env->active_fpu.fp_status);
2288 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2290 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2299 set_float_exception_flags(0, &env->active_fpu.fp_status);
2300 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2302 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2311 set_float_exception_flags(0, &env->active_fpu.fp_status);
2312 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2313 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2316 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2325 set_float_exception_flags(0, &env->active_fpu.fp_status);
2326 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2327 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2330 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2339 set_float_exception_flags(0, &env->active_fpu.fp_status);
2340 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2341 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2344 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2353 set_float_exception_flags(0, &env->active_fpu.fp_status);
2354 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2355 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2358 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2367 set_float_exception_flags(0, &env->active_fpu.fp_status);
2368 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2370 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2379 set_float_exception_flags(0, &env->active_fpu.fp_status);
2380 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2382 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2391 set_float_exception_flags(0, &env->active_fpu.fp_status);
2392 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2394 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2403 set_float_exception_flags(0, &env->active_fpu.fp_status);
2404 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2406 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2415 set_float_exception_flags(0, &env->active_fpu.fp_status);
2416 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2417 env->active_fpu.fp_status);
2420 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2429 set_float_exception_flags(0, &env->active_fpu.fp_status);
2430 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2431 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2434 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2443 set_float_exception_flags(0, &env->active_fpu.fp_status);
2444 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2445 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2448 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2457 set_float_exception_flags(0, &env->active_fpu.fp_status);
2458 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2459 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2462 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2471 set_float_exception_flags(0, &env->active_fpu.fp_status);
2472 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2473 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2476 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2485 set_float_exception_flags(0, &env->active_fpu.fp_status);
2486 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2487 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2490 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2499 set_float_exception_flags(0, &env->active_fpu.fp_status);
2500 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2501 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2504 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2513 set_float_exception_flags(0, &env->active_fpu.fp_status);
2514 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2515 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2518 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2551 set_float_exception_flags(0, &env->active_fpu.fp_status);
2552 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2561 set_float_exception_flags(0, &env->active_fpu.fp_status);
2562 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2571 set_float_exception_flags(0, &env->active_fpu.fp_status);
2572 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2573 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2582 set_float_exception_flags(0, &env->active_fpu.fp_status);
2583 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2584 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2593 set_float_exception_flags(0, &env->active_fpu.fp_status);
2594 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2603 set_float_exception_flags(0, &env->active_fpu.fp_status);
2604 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2614 set_float_exception_flags(0, &env->active_fpu.fp_status);
2615 fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2616 fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
2625 set_float_exception_flags(0, &env->active_fpu.fp_status);
2626 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2627 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2636 set_float_exception_flags(0, &env->active_fpu.fp_status);
2637 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2638 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2648 set_float_exception_flags(0, &env->active_fpu.fp_status);
2649 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2650 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2651 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2652 fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
2665 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2666 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2668 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2677 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2678 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2680 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2694 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2695 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2696 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2698 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
2716 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2717 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2723 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2724 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2737 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2738 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2739 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2740 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2753 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2754 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2761 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2762 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2776 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2777 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2778 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2779 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2792 set_float_exception_flags(0, &env->active_fpu.fp_status);
2793 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2794 fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
2801 set_float_exception_flags(0, &env
2802 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2803 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2815 set_float_exception_flags(0, &env->active_fpu.fp_status);
2816 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2817 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2818 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2819 fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
2826 set_float_exception_flags(0, &env->active_fpu.fp_status);
2827 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2828 fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
2829 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2836 set_float_exception_flags(0, &env->active_fpu.fp_status);
2837 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2838 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2839 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2851 set_float_exception_flags(0, &env->active_fpu.fp_status);
2852 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2853 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2854 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2855 fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
2856 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2857 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2871 set_float_exception_flags(0, &env->active_fpu.fp_status);
2872 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2873 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
2887 set_float_exception_flags(0, &env->active_fpu.fp_status);
2888 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
2889 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
2901 SET_FP_COND(cc, env->active_fpu); \
2903 CLEAR_FP_COND(cc, env->active_fpu); \
2913 SET_FP_COND(cc, env->active_fpu); \
2915 CLEAR_FP_COND(cc, env->active_fpu); \
2934 FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2935 FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
2936 FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2937 FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2938 FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2939 FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2940 FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2941 FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2944 FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2945 FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
2946 FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2947 FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2948 FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2949 FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2950 FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2951 FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2959 SET_FP_COND(cc, env->active_fpu); \
2961 CLEAR_FP_COND(cc, env->active_fpu); \
2971 SET_FP_COND(cc, env->active_fpu); \
2973 CLEAR_FP_COND(cc, env->active_fpu); \
2992 FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
2993 FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
2994 FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2995 FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2996 FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2997 FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2998 FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2999 FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3002 FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
3003 FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
3004 FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3005 FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3006 FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3007 FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3008 FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
3009 FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3023 SET_FP_COND(cc, env->active_fpu); \
3025 CLEAR_FP_COND(cc, env->active_fpu); \
3027 SET_FP_COND(cc + 1, env->active_fpu); \
3029 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3042 SET_FP_COND(cc, env->active_fpu); \
3044 CLEAR_FP_COND(cc, env->active_fpu); \
3046 SET_FP_COND(cc + 1, env->active_fpu); \
3048 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3053 FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
3054 (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
3055 FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
3056 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
3057 FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3058 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3059 FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3060 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3061 FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3062 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3063 FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3064 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3065 FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
3066 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3067 FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3068 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3071 FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
3072 (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
3073 env->active_fpu.fp_status),
3074 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
3075 FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3076 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3077 FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3078 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3079 FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3080 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3081 FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3082 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3083 FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
3084 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3085 FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3086 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
