Lines Matching defs:t4
9044 IRTemp* t5, IRTemp* t4,
9051 breakupV128to32s( t128_1, t7, t6, t5, t4 );
9072 IRTemp t5, IRTemp t4,
9080 binop(Iop_32HLto64, mkexpr(t5), mkexpr(t4)) ),
10017 IRTemp t0, t1, t2, t3, t4, t5, t6, t7;
10035 t0 = t1 = t2 = t3 = t4 = t5 = t6 = t7 = IRTemp_INVALID;
10036 breakupV256to32s( argV, &t7, &t6, &t5, &t4, &t3, &t2, &t1, &t0 );
10048 putYMMRegLane32( rG, 4, CVT(t4) );
10226 IRTemp t0, t1, t2, t3, t4, t5, t6, t7;
10245 t4 = IRTemp_INVALID;
10249 breakupV256to32s( argV, &t7, &t6, &t5, &t4, &t3, &t2, &t1, &t0 );
10258 putYMMRegLane32F( rG, 4, CVT(t4) );
11021 IRTemp t4 = newTemp(Ity_I32);
11038 assign( t4, binop( Iop_And32,
11055 binop(Iop_Or32, mkexpr(t4), mkexpr(t5)),
11127 IRTemp t4 = IRTemp_INVALID;
13156 mmx reg. t4 is the new lane value. t5 is the original
13159 t4 = newTemp(Ity_I16);
13169 assign(t4, getIReg16(eregOfRexRM(pfx,modrm)));
13179 assign(t4, loadLE(Ity_I16, mkexpr(addr)));
13186 case 0: assign(t6, mk64from16s(t3,t2,t1,t4)); break;
13187 case 1: assign(t6, mk64from16s(t3,t2,t4,t0)); break;
13188 case 2: assign(t6, mk64from16s(t3,t4,t1,t0)); break;
13189 case 3: assign(t6, mk64from16s(t4,t2,t1,t0)); break;
13200 t4 = newTemp(Ity_I16);
13205 assign(t4, getIReg16(rE));
13215 assign(t4, loadLE(Ity_I16, mkexpr(addr)));
13221 IRTemp res_vec = math_PINSRW_128( src_vec, t4, lane & 7);
18059 IRTemp t4 = IRTemp_INVALID;
18731 t4 = newTemp(Ity_I64);
18732 assign( t4, binop(Iop_Or64,
18743 mkexpr(t4),
26463 IRTemp t1, t2, t3, t4, t5, t6;
26496 t1 = t2 = t3 = t4 = t5 = t6 = IRTemp_INVALID;
