Lines Matching refs:AMD64RMI_Imm
324 AMD64Instr_Alu64R(Aalu_ADD, AMD64RMI_Imm(n),
332 AMD64Instr_Alu64R(Aalu_SUB, AMD64RMI_Imm(n),
343 addInstr( env, AMD64Instr_Push(AMD64RMI_Imm( (UInt)uimm64 )) );
367 AMD64RMI_Imm(toUInt(e->Iex.Const.con->Ico.U64)),
630 AMD64Instr_Alu64R(Aalu_ADD, AMD64RMI_Imm(bias), tmp));
633 AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(7), tmp));
650 addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(DEFAULT_MXCSR)));
693 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV, AMD64RMI_Imm(3), reg));
698 Aalu_OR, AMD64RMI_Imm(DEFAULT_MXCSR), reg));
725 addInstr(env, AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(3), rrm2));
728 AMD64RMI_Imm(DEFAULT_FPUCW), rrm2));
934 Aalu_AND, AMD64RMI_Imm(0xFF), dst));
938 Aalu_AND, AMD64RMI_Imm(0xFFFF), dst));
1194 Aalu_AND, AMD64RMI_Imm(0xFFFF), lo16));
1209 Aalu_AND, AMD64RMI_Imm(0xFF), lo8));
1254 addInstr(env, AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(0x45), dst));
1285 AMD64RMI_Imm(1), dst));
1377 AMD64RMI_Imm(mask), dst));
1457 AMD64RMI_Imm(63), dst));
1751 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0x4700),dst));
1899 return AMD64RMI_Imm(toUInt(e->Iex.Const.con->Ico.U64));
1903 return AMD64RMI_Imm(e->Iex.Const.con->Ico.U32); break;
1905 return AMD64RMI_Imm(0xFFFF & e->Iex.Const.con->Ico.U16); break;
1907 return AMD64RMI_Imm(0xFF & e->Iex.Const.con->Ico.U8); break;
2060 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(1),dst));
2071 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,AMD64RMI_Imm(0),r));
2126 AMD64RMI* rmi2 = AMD64RMI_Imm(0);
2152 AMD64RMI* rmi2 = AMD64RMI_Imm(0);
2170 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFF),r));
2189 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFFFF),r));
2704 addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));
3224 addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));
3281 AMD64RMI_Imm( ~(UInt)15 ),
3332 AMD64RMI_Imm( ~(UInt)15 ),
