Lines Matching refs:env
159 static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp )
162 vassert(tmp < env->n_vregmap);
163 return env->vregmap[tmp];
167 ISelEnv* env, IRTemp tmp )
170 vassert(tmp < env->n_vregmap);
171 vassert(env->vregmapHI[tmp] != INVALID_HREG);
172 *vrLO = env->vregmap[tmp];
173 *vrHI = env->vregmapHI[tmp];
176 static void addInstr ( ISelEnv* env, AMD64Instr* instr )
178 addHInstr(env->code, instr);
185 static HReg newVRegI ( ISelEnv* env )
187 HReg reg = mkHReg(env->vreg_ctr, HRcInt64, True/*virtual reg*/);
188 env->vreg_ctr++;
192 static HReg newVRegV ( ISelEnv* env )
194 HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/);
195 env->vreg_ctr++;
210 static AMD64RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, IRExpr* e );
211 static AMD64RMI* iselIntExpr_RMI ( ISelEnv* env, IRExpr* e );
213 static AMD64RI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e );
214 static AMD64RI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e );
216 static AMD64RM* iselIntExpr_RM_wrk ( ISelEnv* env, IRExpr* e );
217 static AMD64RM* iselIntExpr_RM ( ISelEnv* env, IRExpr* e );
219 static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e );
220 static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e );
222 static AMD64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e );
223 static AMD64AMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e );
226 ISelEnv* env, IRExpr* e );
228 ISelEnv* env, IRExpr* e );
230 static AMD64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e );
231 static AMD64CondCode iselCondCode ( ISelEnv* env, IRExpr* e );
233 static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e );
234 static HReg iselDblExpr ( ISelEnv* env, IRExpr* e );
236 static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e );
237 static HReg iselFltExpr ( ISelEnv* env, IRExpr* e );
239 static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e );
240 static HReg iselVecExpr ( ISelEnv* env, IRExpr* e );
243 ISelEnv* env, IRExpr* e );
245 ISelEnv* env, IRExpr* e );
320 static void add_to_rsp ( ISelEnv* env, Int n )
323 addInstr(env,
328 static void sub_from_rsp ( ISelEnv* env, Int n )
331 addInstr(env,
337 static void push_uimm64( ISelEnv* env, ULong uimm64 )
343 addInstr( env, AMD64Instr_Push(AMD64RMI_Imm( (UInt)uimm64 )) );
345 HReg tmp = newVRegI(env);
346 addInstr( env, AMD64Instr_Imm64(uimm64, tmp) );
347 addInstr( env, AMD64Instr_Push(AMD64RMI_Reg(tmp)) );
356 static AMD64Instr* iselIntExpr_single_instruction ( ISelEnv* env,
360 vassert(typeOfIRExpr(env->type_env, e) == Ity_I64);
376 HReg src = lookupIRTemp(env, e->Iex.RdTmp.tmp);
393 HReg src = lookupIRTemp(env, e->Iex.Unop.arg->Iex.RdTmp.tmp);
408 void doHelperCall ( ISelEnv* env,
518 vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I64);
520 = iselIntExpr_single_instruction( env, argregs[argreg], args[i] );
530 addInstr(env, fastinstrs[i]);
550 tmpregs[argreg] = newVRegI(env);
551 addInstr(env, mk_iMOVsd_RR( hregAMD64_RBP(), tmpregs[argreg]));
557 vassert(typeOfIRExpr(env->type_env, args[i]) == Ity_I64);
558 tmpregs[argreg] = iselIntExpr_R(env, args[i]);
573 cc = iselCondCode( env, guard );
581 addInstr( env, mk_iMOVsd_RR( tmpregs[i], argregs[i] ) );
587 addInstr(env, AMD64Instr_Call(
601 AMD64AMode* genGuestArrayOffset ( ISelEnv* env, IRRegArray* descr,
622 tmp = newVRegI(env);
623 roff = iselIntExpr_R(env, off);
624 addInstr(env, mk_iMOVsd_RR(roff, tmp));
629 addInstr(env,
632 addInstr(env,
643 void set_SSE_rounding_default ( ISelEnv* env )
650 addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(DEFAULT_MXCSR)));
651 addInstr(env, AMD64Instr_LdMXCSR(zero_rsp));
652 add_to_rsp(env, 8);
658 void set_FPU_rounding_default ( ISelEnv* env )
664 addInstr(env, AMD64Instr_Alu64M(
666 addInstr(env, AMD64Instr_A87LdCW(m8_rsp));
676 void set_SSE_rounding_mode ( ISelEnv* env, IRExpr* mode )
691 HReg reg = newVRegI(env);
693 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV, AMD64RMI_Imm(3), reg));
694 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
695 iselIntExpr_RMI(env, mode), reg));
696 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 13, reg));
697 addInstr(env, AMD64Instr_Alu64R(
699 addInstr(env, AMD64Instr_Push(AMD64RMI_Reg(reg)));
700 addInstr(env, AMD64Instr_LdMXCSR(zero_rsp));
701 add_to_rsp(env, 8);
711 void set_FPU_rounding_mode ( ISelEnv* env, IRExpr* mode )
713 HReg rrm = iselIntExpr_R(env, mode);
714 HReg rrm2 = newVRegI(env);
724 addInstr(env, mk_iMOVsd_RR(rrm, rrm2));
725 addInstr(env, AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(3), rrm2));
726 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 10, rrm2));
727 addInstr(env, AMD64Instr_Alu64R(Aalu_OR,
729 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV,
731 addInstr(env, AMD64Instr_A87LdCW(m8_rsp));
737 static HReg generate_zeroes_V128 ( ISelEnv* env )
739 HReg dst = newVRegV(env);
740 addInstr(env, AMD64Instr_SseReRg(Asse_XOR, dst, dst));
746 static HReg generate_ones_V128 ( ISelEnv* env )
748 HReg dst = newVRegV(env);
749 addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, dst, dst));
757 static HReg do_sse_NotV128 ( ISelEnv* env, HReg src )
759 HReg dst = generate_ones_V128(env);
760 addInstr(env, AMD64Instr_SseReRg(Asse_XOR, src, dst));
798 static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e )
800 HReg r = iselIntExpr_R_wrk(env, e);
811 static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
822 IRType ty = typeOfIRExpr(env->type_env,e);
832 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
837 HReg dst = newVRegI(env);
838 AMD64AMode* amode = iselIntExpr_AMode ( env, e->Iex.Load.addr );
845 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,
850 addInstr(env, AMD64Instr_LoadEX(4,False,amode,dst));
854 addInstr(env, AMD64Instr_LoadEX(2,False,amode,dst));
858 addInstr(env, AMD64Instr_LoadEX(1,False,amode,dst));
873 HReg dst = newVRegI(env);
874 HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg2);
875 addInstr(env, mk_iMOVsd_RR(reg,dst));
876 addInstr(env, AMD64Instr_Unary64(Aun_NEG,dst));
900 HReg dst = newVRegI(env);
901 HReg reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
902 AMD64RMI* rmi = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
903 addInstr(env, mk_iMOVsd_RR(reg,dst));
904 addInstr(env, AMD64Instr_Alu64R(aluOp, rmi, dst));
920 HReg dst = newVRegI(env);
923 HReg regL = iselIntExpr_R(env, e->Iex.Binop.arg1);
924 addInstr(env, mk_iMOVsd_RR(regL,dst));
933 addInstr(env, AMD64Instr_Alu64R(
937 addInstr(env, AMD64Instr_Alu64R(
941 addInstr(env, AMD64Instr_MovxLQ(False, dst, dst));
944 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 56, dst));
945 addInstr(env, AMD64Instr_Sh64(Ash_SAR, 56, dst));
948 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 48, dst));
949 addInstr(env, AMD64Instr_Sh64(Ash_SAR, 48, dst));
952 addInstr(env, AMD64Instr_MovxLQ(True, dst, dst));
969 addInstr(env, AMD64Instr_Sh64(shOp, nshift, dst));
972 HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2);
973 addInstr(env, mk_iMOVsd_RR(regR,hregAMD64_RCX()));
974 addInstr(env, AMD64Instr_Sh64(shOp, 0/* %cl */, dst));
1122 HReg dst = newVRegI(env);
1123 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1124 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1126 addInstr(env, AMD64Instr_MovxLQ(False, argR, argR));
1127 addInstr(env, mk_iMOVsd_RR(argL, hregAMD64_RDI()) );
1128 addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RSI()) );
1129 addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 2 ));
1130 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), dst));
1137 HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1);
1138 HReg dst = newVRegI(env);
1139 HReg src2 = iselIntExpr_R(env, e->Iex.Binop.arg2);
1140 addInstr(env, mk_iMOVsd_RR(src1, dst));
1141 addInstr(env, AMD64Instr_Alu32R(Aalu_CMP, AMD64RMI_Reg(src2), dst));
1142 addInstr(env, AMD64Instr_CMov64(Acc_B, AMD64RM_Reg(src2), dst));
1153 HReg dst = newVRegI(env);
1155 AMD64RM* rmRight = iselIntExpr_RM(env, e->Iex.Binop.arg2);
1158 HReg left64 = iselIntExpr_R(env, e->Iex.Binop.arg1);
1159 addInstr(env, mk_iMOVsd_RR(left64, rdx));
1160 addInstr(env, mk_iMOVsd_RR(left64, rax));
1161 addInstr(env, AMD64Instr_Sh64(Ash_SHR, 32, rdx));
1162 addInstr(env, AMD64Instr_Div(syned, 4, rmRight));
1163 addInstr(env, AMD64Instr_MovxLQ(False, rdx, rdx));
1164 addInstr(env, AMD64Instr_MovxLQ(False, rax, rax));
1165 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, rdx));
1166 addInstr(env, mk_iMOVsd_RR(rax, dst));
1167 addInstr(env, AMD64Instr_Alu64R(Aalu_OR, AMD64RMI_Reg(rdx), dst));
1172 HReg hi32 = newVRegI(env);
1173 HReg lo32 = newVRegI(env);
1174 HReg hi32s = iselIntExpr_R(env, e->Iex.Binop.arg1);
1175 HReg lo32s = iselIntExpr_R(env, e->Iex.Binop.arg2);
1176 addInstr(env, mk_iMOVsd_RR(hi32s, hi32));
1177 addInstr(env, mk_iMOVsd_RR(lo32s, lo32));
1178 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 32, hi32));
1179 addInstr(env, AMD64Instr_MovxLQ(False, lo32, lo32));
1180 addInstr(env, AMD64Instr_Alu64R(
1186 HReg hi16 = newVRegI(env);
1187 HReg lo16 = newVRegI(env);
1188 HReg hi16s = iselIntExpr_R(env, e->Iex.Binop.arg1);
1189 HReg lo16s = iselIntExpr_R(env, e->Iex.Binop.arg2);
1190 addInstr(env, mk_iMOVsd_RR(hi16s, hi16));
1191 addInstr(env, mk_iMOVsd_RR(lo16s, lo16));
1192 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 16, hi16));
1193 addInstr(env, AMD64Instr_Alu64R(
1195 addInstr(env, AMD64Instr_Alu64R(
1201 HReg hi8 = newVRegI(env);
1202 HReg lo8 = newVRegI(env);
1203 HReg hi8s = iselIntExpr_R(env, e->Iex.Binop.arg1);
1204 HReg lo8s = iselIntExpr_R(env, e->Iex.Binop.arg2);
1205 addInstr(env, mk_iMOVsd_RR(hi8s, hi8));
1206 addInstr(env, mk_iMOVsd_RR(lo8s, lo8));
1207 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 8, hi8));
1208 addInstr(env, AMD64Instr_Alu64R(
1210 addInstr(env, AMD64Instr_Alu64R(
1221 HReg a32 = newVRegI(env);
1222 HReg b32 = newVRegI(env);
1223 HReg a32s = iselIntExpr_R(env, e->Iex.Binop.arg1);
1224 HReg b32s = iselIntExpr_R(env, e->Iex.Binop.arg2);
1237 addInstr(env, mk_iMOVsd_RR(a32s, a32));
1238 addInstr(env, mk_iMOVsd_RR(b32s, b32));
1239 addInstr(env, AMD64Instr_Sh64(Ash_SHL, shift, a32));
1240 addInstr(env, AMD64Instr_Sh64(Ash_SHL, shift, b32));
1241 addInstr(env, AMD64Instr_Sh64(shr_op, shift, a32));
1242 addInstr(env, AMD64Instr_Sh64(shr_op, shift, b32));
1243 addInstr(env, AMD64Instr_Alu64R(Aalu_MUL, AMD64RMI_Reg(a32), b32));
1248 HReg fL = iselDblExpr(env, e->Iex.Binop.arg1);
1249 HReg fR = iselDblExpr(env, e->Iex.Binop.arg2);
1250 HReg dst = newVRegI(env);
1251 addInstr(env, AMD64Instr_SseUComIS(8,fL,fR,dst));
1254 addInstr(env, AMD64Instr_Alu64R(Aalu_AND, AMD64RMI_Imm(0x45), dst));
1261 HReg rf = iselDblExpr(env, e->Iex.Binop.arg2);
1262 HReg dst = newVRegI(env);
1263 set_SSE_rounding_mode( env, e->Iex.Binop.arg1 );
1264 addInstr(env, AMD64Instr_SseSF2SI( 8, szD, rf, dst ));
1265 set_SSE_rounding_default(env);
1281 HReg dst = newVRegI(env);
1282 HReg src = iselIntExpr_R(env, expr64);
1283 addInstr(env, mk_iMOVsd_RR(src,dst) );
1284 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
1296 HReg dst = newVRegI(env);
1297 AMD64AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] );
1298 addInstr(env, AMD64Instr_LoadEX(1,False,amode,dst));
1309 HReg dst = newVRegI(env);
1310 AMD64AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] );
1311 addInstr(env, AMD64Instr_LoadEX(2,False,amode,dst));
1335 HReg dst = newVRegI(env);
1336 HReg reg = iselIntExpr_R(env, argL);
1337 AMD64RMI* rmi = iselIntExpr_RMI(env, argR);
1338 addInstr(env, mk_iMOVsd_RR(reg,dst));
1339 addInstr(env, AMD64Instr_Alu32R(aluOp, rmi, dst));
1349 HReg dst = newVRegI(env);
1350 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1351 addInstr(env, AMD64Instr_MovxLQ(e->Iex.Unop.op == Iop_32Sto64,
1357 iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
1362 iselInt128Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
1370 HReg dst = newVRegI(env);
1371 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1375 addInstr(env, mk_iMOVsd_RR(src,dst) );
1376 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
1385 HReg dst = newVRegI(env);
1386 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1390 env, mk_iMOVsd_RR(src,dst) );
1391 addInstr(env, AMD64Instr_Sh64(Ash_SHL, amt, dst));
1392 addInstr(env, AMD64Instr_Sh64(Ash_SAR, amt, dst));
1399 HReg dst = newVRegI(env);
1400 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1401 addInstr(env, mk_iMOVsd_RR(src,dst) );
1402 addInstr(env, AMD64Instr_Unary64(Aun_NOT,dst));
1408 HReg dst = newVRegI(env);
1409 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1417 addInstr(env, mk_iMOVsd_RR(src,dst) );
1418 addInstr(env, AMD64Instr_Sh64(Ash_SHR, shift, dst));
1424 HReg dst = newVRegI(env);
1425 AMD64CondCode cond = iselCondCode(env, e->Iex.Unop.arg);
1426 addInstr(env, AMD64Instr_Set64(cond,dst));
1434 HReg dst = newVRegI(env);
1435 AMD64CondCode cond = iselCondCode(env, e->Iex.Unop.arg);
1436 addInstr(env, AMD64Instr_Set64(cond,dst));
1437 addInstr(env, AMD64Instr_Sh64(Ash_SHL, 63, dst));
1438 addInstr(env, AMD64Instr_Sh64(Ash_SAR, 63, dst));
1443 HReg dst = newVRegI(env);
1444 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1445 addInstr(env, AMD64Instr_Bsfr64(True,src,dst));
1452 HReg tmp = newVRegI(env);
1453 HReg dst = newVRegI(env);
1454 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1455 addInstr(env, AMD64Instr_Bsfr64(False,src,tmp));
1456 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,
1458 addInstr(env, AMD64Instr_Alu64R(Aalu_SUB,
1464 HReg dst = newVRegI(env);
1465 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1466 addInstr(env, mk_iMOVsd_RR(src,dst));
1467 addInstr(env, AMD64Instr_Unary64(Aun_NEG,dst));
1468 addInstr(env, AMD64Instr_Alu64R(Aalu_OR,
1470 addInstr(env, AMD64Instr_Sh64(Ash_SAR, 63, dst));
1475 HReg src = newVRegI(env);
1476 HReg dst = newVRegI(env);
1477 HReg pre = iselIntExpr_R(env, e->Iex.Unop.arg);
1478 addInstr(env, mk_iMOVsd_RR(pre,src));
1479 addInstr(env, AMD64Instr_MovxLQ(False, src, src));
1480 addInstr(env, mk_iMOVsd_RR(src,dst));
1481 addInstr(env, AMD64Instr_Unary64(Aun_NEG,dst));
1482 addInstr(env, AMD64Instr_Alu64R(Aalu_OR,
1484 addInstr(env, AMD64Instr_Sh64(Ash_SAR, 63, dst));
1492 HReg dst = newVRegI(env);
1493 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1494 addInstr(env, mk_iMOVsd_RR(src, dst));
1495 addInstr(env, AMD64Instr_Unary64(Aun_NEG, dst));
1496 addInstr(env, AMD64Instr_Alu64R(Aalu_OR, AMD64RMI_Reg(src), dst));
1501 HReg dst = newVRegI(env);
1502 HReg vec = iselVecExpr(env, e->Iex.Unop.arg);
1504 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vec, rsp_m16));
1505 addInstr(env, AMD64Instr_LoadEX(4, False/*z-widen*/, rsp_m16, dst));
1512 HReg dst = newVRegI(env);
1515 HReg vec = iselVecExpr(env, e->Iex.Unop.arg);
1518 addInstr(env, AMD64Instr_SseLdSt(False/*store*/,
1520 addInstr(env, AMD64Instr_Alu64R( Aalu_MOV,
1528 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
1540 HReg dst = newVRegI(env);
1544 addInstr(env, AMD64Instr_SseLdSt(False/*store*/,
1546 addInstr(env, AMD64Instr_Alu64R( Aalu_MOV,
1556 HReg dst = newVRegI(env);
1557 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
1559 set_SSE_rounding_default(env);
1560 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, src, m8_rsp));
1561 addInstr(env, AMD64Instr_Alu64R(
1571 HReg dst = newVRegI(env);
1572 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
1574 set_SSE_rounding_default(env);
1575 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 4, src, m8_rsp));
1576 addInstr(env, AMD64Instr_LoadEX(4, False/*unsigned*/, m8_rsp, dst ));
1587 return iselIntExpr_R(env, e->Iex.Unop.arg);
1610 HReg dst = newVRegI(env);
1611 HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
1612 addInstr(env, mk_iMOVsd_RR(arg, hregAMD64_RDI()) );
1613 addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 1 ));
1614 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), dst));
1624 HReg dst = newVRegI(env);
1625 addInstr(env, AMD64Instr_Alu64R(
1634 HReg dst = newVRegI(env);
1635 addInstr(env, AMD64Instr_LoadEX(
1648 env, e->Iex.GetI.descr,
1650 HReg dst = newVRegI(env);
1652 addInstr(env, AMD64Instr_LoadEX( 1, False, am, dst ));
1656 addInstr(env, AMD64Instr_Alu64R( Aalu_MOV, AMD64RMI_Mem(am), dst ));
1664 HReg dst = newVRegI(env);
1673 doHelperCall( env, False, NULL, e->Iex.CCall.cee, e->Iex.CCall.args );
1678 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), dst));
1680 addInstr(env, AMD64Instr_MovxLQ(False, hregAMD64_RAX(), dst));
1689 HReg r = newVRegI(env);
1690 addInstr(env, AMD64Instr_Imm64(e->Iex.Const.con->Ico.U64, r));
1693 AMD64RMI* rmi = iselIntExpr_RMI ( env, e );
1694 HReg r = newVRegI(env);
1695 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV, rmi, r));
1702 && typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8) {
1704 HReg rX = iselIntExpr_R(env, e->Iex.Mux0X.exprX);
1705 AMD64RM* r0 = iselIntExpr_RM(env, e->Iex.Mux0X.expr0);
1706 HReg dst = newVRegI(env);
1707 addInstr(env, mk_iMOVsd_RR(rX,dst));
1708 r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
1709 addInstr(env, AMD64Instr_Test64(0xFF, r8));
1710 addInstr(env, AMD64Instr_CMov64(Acc_Z,r0,dst));
1724 HReg arg1 = iselDblExpr(env, triop->arg2);
1725 HReg arg2 = iselDblExpr(env, triop->arg3);
1726 HReg dst = newVRegI(env);
1727 addInstr(env, AMD64Instr_A87Free(2));
1730 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg2, m8_rsp));
1731 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
1734 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg1, m8_rsp));
1735 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
1739 addInstr(env, AMD64Instr_A87FpOp(Afp_PREM));
1742 addInstr(env, AMD64Instr_A87FpOp(Afp_PREM1));
1749 addInstr(env, AMD64Instr_A87StSW(m8_rsp));
1750 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,AMD64RMI_Mem(m8_rsp),dst));
1751 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0x4700),dst));
1779 static AMD64AMode* iselIntExpr_AMode ( ISelEnv* env, IRExpr* e )
1781 AMD64AMode* am = iselIntExpr_AMode_wrk(env, e);
1787 static AMD64AMode* iselIntExpr_AMode_wrk ( ISelEnv* env, IRExpr* e )
1791 IRType ty = typeOfIRExpr(env->type_env,e);
1819 HReg r1 = iselIntExpr_R(env, expr1);
1820 HReg r2 = iselIntExpr_R(env, expr2);
1835 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1);
1836 HReg r2 = iselIntExpr_R(env, e->Iex.Binop.arg2->Iex.Binop.arg1 );
1847 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1);
1857 HReg r1 = iselIntExpr_R(env, e);
1868 static AMD64RMI* iselIntExpr_RMI ( ISelEnv* env, IRExpr* e )
1870 AMD64RMI* rmi = iselIntExpr_RMI_wrk(env, e);
1888 static AMD64RMI* iselIntExpr_RMI_wrk ( ISelEnv* env, IRExpr* e )
1890 IRType ty = typeOfIRExpr(env->type_env,e);
1922 AMD64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr);
1928 HReg r = iselIntExpr_R ( env, e );
1940 static AMD64RI* iselIntExpr_RI ( ISelEnv* env, IRExpr* e )
1942 AMD64RI* ri = iselIntExpr_RI_wrk(env, e);
1957 static AMD64RI* iselIntExpr_RI_wrk ( ISelEnv* env, IRExpr* e )
1959 IRType ty = typeOfIRExpr(env->type_env,e);
1984 HReg r = iselIntExpr_R ( env, e );
1996 static AMD64RM* iselIntExpr_RM ( ISelEnv* env, IRExpr* e )
1998 AMD64RM* rm = iselIntExpr_RM_wrk(env, e);
2014 static AMD64RM* iselIntExpr_RM_wrk ( ISelEnv* env, IRExpr* e )
2016 IRType ty = typeOfIRExpr(env->type_env,e);
2029 HReg r = iselIntExpr_R ( env, e );
2041 static AMD64CondCode iselCondCode ( ISelEnv* env, IRExpr* e )
2044 return iselCondCode_wrk(env,e);
2048 static AMD64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e )
2053 vassert(typeOfIRExpr(env->type_env,e) == Ity_I1);
2057 HReg r64 = lookupIRTemp(env, e->Iex.RdTmp.tmp);
2058 HReg dst = newVRegI(env);
2059 addInstr(env, mk_iMOVsd_RR(r64,dst));
2060 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(1),dst));
2070 r = newVRegI(env);
2071 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,AMD64RMI_Imm(0),r));
2072 addInstr(env, AMD64Instr_Alu64R(Aalu_XOR,AMD64RMI_Reg(r),r));
2079 return 1 ^ iselCondCode(env, e->Iex.Unop.arg);
2086 HReg reg = iselIntExpr_R(env, e->Iex.Unop.arg);
2087 addInstr(env, AMD64Instr_Test64(1,reg));
2095 HReg reg = iselIntExpr_R(env, e->Iex.Unop.arg);
2096 addInstr(env, AMD64Instr_Test64(1,reg));
2105 HReg r = iselIntExpr_R(env, e->Iex.Unop.arg);
2106 addInstr(env, AMD64Instr_Test64(0xFF,r));
2115 HReg r = iselIntExpr_R(env, e->Iex.Unop.arg);
2116 addInstr(env, AMD64Instr_Test64(0xFFFF,r));
2125 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg);
2127 addInstr(env, AMD64Instr_Alu32R(Aalu_CMP,rmi2,r1));
2139 HReg r0 = iselIntExpr_R(env, mi.bindee[0]);
2140 AMD64RMI* rmi1 = iselIntExpr_RMI(env, mi.bindee[1]);
2141 HReg tmp = newVRegI(env);
2142 addInstr(env, mk_iMOVsd_RR(r0, tmp));
2143 addInstr(env, AMD64Instr_Alu64R(Aalu_OR,rmi1,tmp));
2151 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg);
2153 addInstr(env, AMD64Instr_Alu64R(Aalu_CMP,rmi2,r1));
2165 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1);
2166 AMD64RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
2167 HReg r = newVRegI(env);
2168 addInstr(env, mk_iMOVsd_RR(r1,r));
2169 addInstr(env, AMD64Instr_Alu64R(Aalu_XOR,rmi2,r));
2170 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFF),r));
2184 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1);
2185 AMD64RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
2186 HReg r = newVRegI(env);
2187 addInstr(env, mk_iMOVsd_RR(r1,r));
2188 addInstr(env, AMD64Instr_Alu64R(Aalu_XOR,rmi2,r));
2189 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(0xFFFF),r));
2205 HReg tmp = newVRegI(env);
2210 doHelperCall( env, False, NULL, cal->Iex.CCall.cee, cal->Iex.CCall.args );
2211 addInstr(env, AMD64Instr_Imm64(con->Iex.Const.con->Ico.U64, tmp));
2212 addInstr(env, AMD64Instr_Alu64R(Aalu_CMP,
2227 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1);
2228 AMD64RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
2229 addInstr(env, AMD64Instr_Alu64R(Aalu_CMP,rmi2,r1));
2251 HReg r1 = iselIntExpr_R(env, e->Iex.Binop.arg1);
2252 AMD64RMI* rmi2 = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
2253 addInstr(env, AMD64Instr_Alu32R(Aalu_CMP,rmi2,r1));
2280 ISelEnv* env, IRExpr* e )
2282 iselInt128Expr_wrk(rHi, rLo, env, e);
2294 ISelEnv* env, IRExpr* e )
2297 vassert(typeOfIRExpr(env->type_env,e) == Ity_I128);
2301 lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp);
2314 env);
2315 HReg tHi = newVRegI(env);
2317 AMD64RM* rmLeft = iselIntExpr_RM(env, e->Iex.Binop.arg1);
2318 HReg rRight = iselIntExpr_R(env, e->Iex.Binop.arg2);
2319 addInstr(env, mk_iMOVsd_RR(rRight, hregAMD64_RAX()));
2320 addInstr(env, AMD64Instr_MulL(syned, rmLeft));
2322 addInstr(env, mk_iMOVsd_RR(hregAMD64_RDX(), tHi));
2323 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), tLo));
2335 HReg tLo = newVRegI(env);
2336 HReg tHi = newVRegI(env);
2338 AMD64RM* rmRight = iselIntExpr_RM(env, e->Iex.Binop.arg2);
2339 iselInt128Expr(&sHi,&sLo, env, e->Iex.Binop.arg1);
2340 addInstr(env, mk_iMOVsd_RR(sHi, hregAMD64_RDX()));
2341 addInstr(env, mk_iMOVsd_RR(sLo, hregAMD64_RAX()));
2342 addInstr(env, AMD64Instr_Div(syned, 8, rmRight));
2343 addInstr(env, mk_iMOVsd_RR(hregAMD64_RDX(), tHi));
2344 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(), tLo));
2352 *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1);
2353 *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2);
2373 static HReg iselFltExpr ( ISelEnv* env, IRExpr* e )
2375 HReg r = iselFltExpr_wrk( env, e );
2385 static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e )
2387 IRType ty = typeOfIRExpr(env->type_env,e);
2391 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
2396 HReg res = newVRegV(env);
2398 am = iselIntExpr_AMode(env, e->Iex.Load.addr);
2399 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 4, res, am));
2408 HReg dst = newVRegV(env);
2409 HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
2410 set_SSE_rounding_mode( env, e->Iex.Binop.arg1 );
2411 addInstr(env, AMD64Instr_SseSDSS(True/*D->S*/,src,dst));
2412 set_SSE_rounding_default( env );
2419 HReg res = newVRegV(env);
2420 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 4, res, am ));
2428 HReg dst = newVRegV(env);
2429 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
2431 addInstr(env, AMD64Instr_Store(4, src, m4_rsp));
2432 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 4, dst, m4_rsp ));
2438 HReg arg = iselFltExpr(env, e->Iex.Binop.arg2);
2439 HReg dst = newVRegV(env);
2445 set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
2447 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 4, arg, m8_rsp));
2448 addInstr(env, AMD64Instr_A87Free(1));
2449 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 4));
2450 addInstr(env, AMD64Instr_A87FpOp(Afp_ROUND));
2451 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 4));
2452 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 4, dst, m8_rsp));
2455 set_FPU_rounding_default( env );
2493 static HReg iselDblExpr ( ISelEnv* env, IRExpr* e )
2495 HReg r = iselDblExpr_wrk( env, e );
2505 static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
2507 IRType ty = typeOfIRExpr(env->type_env,e);
2512 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
2517 HReg res = newVRegV(env);
2518 HReg tmp = newVRegI(env);
2532 addInstr(env, AMD64Instr_Imm64(u.u64, tmp));
2533 addInstr(env, AMD64Instr_Push(AMD64RMI_Reg(tmp)));
2534 addInstr(env, AMD64Instr_SseLdSt(
2538 add_to_rsp(env, 8);
2544 HReg res = newVRegV(env);
2546 am = iselIntExpr_AMode(env, e->Iex.Load.addr);
2547 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 8, res, am ));
2554 HReg res = newVRegV(env);
2555 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 8, res, am ));
2562 env, e->Iex.GetI.descr,
2564 HReg res = newVRegV(env);
2565 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 8, res, am ));
2580 HReg dst = newVRegV(env);
2581 HReg argL = iselDblExpr(env, triop->arg2);
2582 HReg argR = iselDblExpr(env, triop->arg3);
2583 addInstr(env, mk_vMOVsd_RR(argL, dst));
2586 addInstr(env, AMD64Instr_Sse64FLo(op, argR, dst));
2593 HReg arg = iselDblExpr(env, e->Iex.Binop.arg2);
2594 HReg dst = newVRegV(env);
2600 set_FPU_rounding_mode( env, e->Iex.Binop.arg1 );
2602 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg, m8_rsp));
2603 addInstr(env, AMD64Instr_A87Free(1));
2604 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
2605 addInstr(env, AMD64Instr_A87FpOp(Afp_ROUND));
2606 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));
2607 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
2610 set_FPU_rounding_default( env );
2625 HReg arg1 = iselDblExpr(env, triop->arg2);
2626 HReg arg2 = iselDblExpr(env, triop->arg3);
2627 HReg dst = newVRegV(env);
2631 addInstr(env, AMD64Instr_A87Free(2));
2634 addInstr(env, AMD64Instr_SseLdSt(
2636 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
2639 addInstr(env, AMD64Instr_SseLdSt(
2641 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
2648 addInstr(env, AMD64Instr_A87FpOp(Afp_SCALE));
2651 addInstr(env, AMD64Instr_A87FpOp(Afp_ATAN));
2654 addInstr(env, AMD64Instr_A87FpOp(Afp_YL2X));
2657 addInstr(env, AMD64Instr_A87FpOp(Afp_YL2XP1));
2660 addInstr(env, AMD64Instr_A87FpOp(Afp_PREM));
2663 addInstr(env, AMD64Instr_A87FpOp(Afp_PREM1));
2670 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));
2671 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
2676 HReg dst = newVRegV(env);
2677 HReg src = iselIntExpr_R(env, e->Iex.Binop.arg2);
2678 set_SSE_rounding_mode( env, e->Iex.Binop.arg1 );
2679 addInstr(env, AMD64Instr_SseSI2SF( 8, 8, src, dst ));
2680 set_SSE_rounding_default( env );
2685 HReg dst = newVRegV(env);
2686 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
2687 set_SSE_rounding_default( env );
2688 addInstr(env, AMD64Instr_SseSI2SF( 4, 8, src, dst ));
2698 HReg r1 = newVRegI(env);
2699 HReg dst = newVRegV(env);
2700 HReg tmp = newVRegV(env);
2701 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
2703 addInstr(env, mk_vMOVsd_RR(src,tmp));
2704 addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));
2705 addInstr(env, AMD64Instr_Imm64( 1ULL<<63, r1 ));
2706 addInstr(env, AMD64Instr_Push(AMD64RMI_Reg(r1)));
2707 addInstr(env, AMD64Instr_SseLdSt(True, 16, dst, rsp0));
2710 addInstr(env, AMD64Instr_SseReRg(Asse_XOR, tmp, dst));
2712 addInstr(env, AMD64Instr_SseReRg(Asse_ANDN, tmp, dst));
2714 add_to_rsp(env, 16);
2730 HReg arg = iselDblExpr(env, e->Iex.Binop.arg2);
2731 HReg dst = newVRegV(env);
2733 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, arg, m8_rsp));
2734 addInstr(env, AMD64Instr_A87Free(nNeeded));
2735 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, True/*push*/, 8));
2738 addInstr(env, AMD64Instr_A87FpOp(fpop));
2741 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));
2743 addInstr(env, AMD64Instr_A87PushPop(m8_rsp, False/*pop*/, 8));
2744 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
2752 //.. HReg dst = newVRegF(env);
2753 //.. HReg ri = iselIntExpr_R(env, e->Iex.Unop.arg);
2754 //.. addInstr(env, X86Instr_Push(X86RMI_Reg(ri)));
2755 //.. set_FPU_rounding_default(env);
2756 //.. addInstr(env, X86Instr_FpLdStI(
2759 //.. add_to_esp(env, 4);
2766 HReg dst = newVRegV(env);
2767 env, e->Iex.Unop.arg);
2769 set_SSE_rounding_default(env);
2770 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, src, m8_rsp));
2771 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 8, dst, m8_rsp));
2776 HReg f64 = newVRegV(env);
2778 set_SSE_rounding_default(env);
2779 f32 = iselFltExpr(env, e->Iex.Unop.arg);
2780 addInstr(env, AMD64Instr_SseSDSS(False/*S->D*/, f32, f64));
2792 vassert(typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8);
2793 r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
2794 rX = iselDblExpr(env, e->Iex.Mux0X.exprX);
2795 r0 = iselDblExpr(env, e->Iex.Mux0X.expr0);
2796 dst = newVRegV(env);
2797 addInstr(env, mk_vMOVsd_RR(rX,dst));
2798 addInstr(env, AMD64Instr_Test64(0xFF, r8));
2799 addInstr(env, AMD64Instr_SseCMov(Acc_Z,r0,dst));
2812 static HReg iselVecExpr ( ISelEnv* env, IRExpr* e )
2814 HReg r = iselVecExpr_wrk( env, e );
2825 static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
2830 IRType ty = typeOfIRExpr(env->type_env,e);
2835 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
2839 HReg dst = newVRegV(env);
2840 addInstr(env, AMD64Instr_SseLdSt(
2851 HReg dst = newVRegV(env);
2852 AMD64AMode* am = iselIntExpr_AMode(env, e->Iex.Load.addr);
2853 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, am ));
2858 HReg dst = newVRegV(env);
2862 dst = generate_zeroes_V128(env);
2865 dst = generate_ones_V128(env);
2870 push_uimm64(env, bitmask8_to_bytemask64(
2873 push_uimm64(env, bitmask8_to_bytemask64(
2876 addInstr(env, AMD64Instr_SseLdSt( True/*load*/, 16, dst, rsp0 ));
2877 add_to_rsp(env, 16);
2888 HReg arg = iselVecExpr(env, e->Iex.Unop.arg);
2889 return do_sse_NotV128(env, arg);
2908 HReg arg = iselVecExpr(env, e->Iex.Unop.arg);
2909 HReg tmp = generate_zeroes_V128(env);
2910 HReg dst = newVRegV(env);
2911 addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, arg, tmp));
2912 tmp = do_sse_NotV128(env, tmp);
2913 addInstr(env, AMD64Instr_SseShuf(0xB1, tmp, dst));
2914 addInstr(env, AMD64Instr_SseReRg(Asse_OR, tmp, dst));
2923 HReg arg = iselVecExpr(env, e->Iex.Unop.arg);
2924 HReg tmp = newVRegV(env);
2925 HReg zero = generate_zeroes_V128(env);
2927 addInstr(env, mk_vMOVsd_RR(arg, tmp));
2928 addInstr(env, AMD64Instr_SseReRg(op, zero, tmp));
2929 dst = do_sse_NotV128(env, tmp);
2938 HReg arg = iselVecExpr(env, e->Iex.Unop.arg);
2939 HReg dst = newVRegV(env);
2940 addInstr(env, AMD64Instr_Sse32Fx4(op, arg, dst));
2947 HReg arg = iselVecExpr(env, e->Iex.Unop.arg);
2948 HReg dst = newVRegV(env);
2949 addInstr(env, AMD64Instr_Sse64Fx2(op, arg, dst));
2964 HReg arg = iselVecExpr(env, e->Iex.Unop.arg);
2965 HReg dst = newVRegV(env);
2966 addInstr(env, mk_vMOVsd_RR(arg, dst));
2967 addInstr(env, AMD64Instr_Sse32FLo(op, arg, dst));
2980 HReg arg = iselVecExpr(env, e->Iex.Unop.arg);
2981 HReg dst = newVRegV(env);
2982 addInstr(env, mk_vMOVsd_RR(arg, dst));
2983 addInstr(env, AMD64Instr_Sse64FLo(op, arg, dst));
2988 HReg dst = newVRegV(env);
2990 AMD64RI* ri = iselIntExpr_RI(env, e->Iex.Unop.arg);
2991 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, ri, rsp_m32));
2992 addInstr(env, AMD64Instr_SseLdzLO(4, dst, rsp_m32));
2997 HReg dst = newVRegV(env);
2999 AMD64RMI* rmi = iselIntExpr_RMI(env, e->Iex.Unop.arg);
3000 addInstr(env, AMD64Instr_Push(rmi));
3001 addInstr(env, AMD64Instr_SseLdzLO(8, dst, rsp0));
3002 add_to_rsp(env, 8);
3009 iselDVecExpr(&vHi, &vLo, env, e->Iex.Unop.arg);
3023 HReg dst = newVRegV(env);
3024 HReg srcV = iselVecExpr(env, e->Iex.Binop.arg1);
3025 HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2);
3027 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, srcV, rsp_m16));
3028 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, AMD64RI_Reg(srcI), rsp_m16));
3029 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, dst, rsp_m16));
3035 HReg dst = newVRegV(env);
3036 HReg srcV = iselVecExpr(env, e->Iex.Binop.arg1);
3037 HReg srcI = iselIntExpr_R(env, e->Iex.Binop.arg2);
3039 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, srcV, rsp_m16));
3040 addInstr(env, AMD64Instr_Store(4, srcI, rsp_m16));
3041 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, dst, rsp_m16));
3049 AMD64RI* qHi = iselIntExpr_RI(env, e->Iex.Binop.arg1);
3050 AMD64RI* qLo = iselIntExpr_RI(env, e->Iex.Binop.arg2);
3051 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, qHi, m8_rsp));
3052 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, qLo, m16_rsp));
3053 HReg dst = newVRegV(env);
3055 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, dst, m16_rsp));
3071 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);
3072 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3073 HReg dst = newVRegV(env);
3074 addInstr(env, mk_vMOVsd_RR(argL, dst));
3075 addInstr(env, AMD64Instr_Sse32Fx4(op, argR, dst));
3091 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);
3092 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3093 HReg dst = newVRegV(env);
3094 addInstr(env, mk_vMOVsd_RR(argL, dst));
3095 addInstr(env, AMD64Instr_Sse64Fx2(op, argR, dst));
3110 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);
3111 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3112 HReg dst = newVRegV(env);
3113 addInstr(env, mk_vMOVsd_RR(argL, dst));
3114 addInstr(env, AMD64Instr_Sse32FLo(op, argR, dst));
3129 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);
3130 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3131 HReg dst = newVRegV(env);
3132 addInstr(env, mk_vMOVsd_RR(argL, dst));
3133 addInstr(env, AMD64Instr_Sse64FLo(op, argR, dst));
3197 HReg arg1 = iselVecExpr(env, e->Iex.Binop.arg1);
3198 HReg arg2 = iselVecExpr(env, e->Iex.Binop.arg2);
3199 HReg dst = newVRegV(env);
3201 addInstr(env, mk_vMOVsd_RR(arg2, dst));
3202 addInstr(env, AMD64Instr_SseReRg(op, arg1, dst));
3204 addInstr(env, mk_vMOVsd_RR(arg1, dst));
3205 addInstr(env, AMD64Instr_SseReRg(op, arg2, dst));
3219 HReg greg = iselVecExpr(env, e->Iex.Binop.arg1);
3220 AMD64RMI* rmi = iselIntExpr_RMI(env, e->Iex.Binop.arg2);
3222 HReg ereg = newVRegV(env);
3223 HReg dst = newVRegV(env);
3224 addInstr(env, AMD64Instr_Push(AMD64RMI_Imm(0)));
3225 addInstr(env, AMD64Instr_Push(rmi));
3226 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, ereg, rsp0));
3227 addInstr(env, mk_vMOVsd_RR(greg, dst));
3228 addInstr(env, AMD64Instr_SseReRg(op, ereg, dst));
3229 add_to_rsp(env, 16);
3270 HReg dst = newVRegV(env);
3271 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);
3272 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3273 HReg argp = newVRegI(env);
3275 sub_from_rsp(env, 112);
3277 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(48, hregAMD64_RSP()),
3280 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
3288 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(0, argp),
3290 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(16, argp),
3292 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(32, argp),
3298 addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argL,
3300 addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argR,
3303 addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 3 ));
3306 addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 16, dst,
3309 add_to_rsp(env, 112);
3321 HReg dst = newVRegV(env);
3322 HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);
3323 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
3324 HReg argp = newVRegI(env);
3326 sub_from_rsp(env, 112);
3328 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(48, hregAMD64_RSP()),
3331 addInstr(env, AMD64Instr_Alu64R(Aalu_AND,
3338 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(0, argp),
3340 addInstr(env, AMD64Instr_Lea64(AMD64AMode_IR(16, argp),
3345 addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argL,
3348 addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RDX()));
3351 addInstr(env, AMD64Instr_Call( Acc_ALWAYS, (ULong)fn, 3 ));
3354 addInstr(env, AMD64Instr_SseLdSt(True/*isLoad*/, 16, dst,
3357 add_to_rsp(env, 112);
3367 HReg r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
3368 HReg rX = iselVecExpr(env, e->Iex.Mux0X.exprX);
3369 HReg r0 = iselVecExpr(env, e->Iex.Mux0X.expr0);
3370 HReg dst = newVRegV(env);
3371 addInstr(env, mk_vMOVsd_RR(rX,dst));
3372 addInstr(env, AMD64Instr_Test64(0xFF, r8));
3373 addInstr(env, AMD64Instr_SseCMov(Acc_Z,r0,dst));
3379 LibVEX_ppVexHwCaps(VexArchAMD64, env->hwcaps));
3390 ISelEnv* env, IRExpr* e )
3392 iselDVecExpr_wrk( rHi, rLo, env, e );
3405 ISelEnv* env, IRExpr* e )
3408 IRType ty = typeOfIRExpr(env->type_env,e);
3415 lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp);
3420 HReg vHi = newVRegV(env);
3421 HReg vLo = newVRegV(env);
3425 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, am0));
3426 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
3433 HReg vHi = newVRegV(env);
3434 HReg vLo = newVRegV(env);
3435 HReg rA = iselIntExpr_R(env, e->Iex.Load.addr);
3438 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, am0));
3439 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, am16));
3449 HReg vHi = generate_zeroes_V128(env);
3450 HReg vLo = newVRegV(env);
3451 addInstr(env, mk_vMOVsd_RR(vHi, vLo));
3466 iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg);
3467 *rHi = do_sse_NotV128(env, argHi);
3468 *rLo = do_sse_NotV128(env, argLo);
3478 iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg);
3479 HReg dstHi = newVRegV(env);
3480 HReg dstLo = newVRegV(env);
3481 addInstr(env, AMD64Instr_Sse32Fx4(op, argHi, dstHi));
3482 addInstr(env, AMD64Instr_Sse32Fx4(op, argLo, dstLo));
3492 iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg);
3493 HReg dstHi = newVRegV(env);
3494 HReg dstLo = newVRegV(env);
3495 addInstr(env, AMD64Instr_Sse64Fx2(op, argHi, dstHi));
3496 addInstr(env, AMD64Instr_Sse64Fx2(op, argLo, dstLo));
3508 iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg);
3509 HReg tmpHi = generate_zeroes_V128(env);
3510 HReg tmpLo = newVRegV(env);
3511 addInstr(env, mk_vMOVsd_RR(tmpHi, tmpLo));
3512 HReg dstHi = newVRegV(env);
3513 HReg dstLo = newVRegV(env);
3514 addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, argHi, tmpHi));
3515 addInstr(env, AMD64Instr_SseReRg(Asse_CMPEQ32, argLo, tmpLo));
3516 tmpHi = do_sse_NotV128(env, tmpHi);
3517 tmpLo = do_sse_NotV128(env, tmpLo);
3518 addInstr(env, AMD64Instr_SseShuf(0xB1, tmpHi, dstHi));
3519 addInstr(env, AMD64Instr_SseShuf(0xB1, tmpLo, dstLo));
3520 addInstr(env, AMD64Instr_SseReRg(Asse_OR, tmpHi, dstHi));
3521 addInstr(env, AMD64Instr_SseReRg(Asse_OR, tmpLo, dstLo));
3531 iselDVecExpr(&argHi, &argLo, env, e->Iex.Unop.arg);
3532 HReg tmpHi = newVRegV(env);
3533 HReg tmpLo = newVRegV(env);
3534 HReg zero = generate_zeroes_V128(env);
3536 addInstr(env, mk_vMOVsd_RR(argHi, tmpHi));
3537 addInstr(env, mk_vMOVsd_RR(argLo, tmpLo));
3538 addInstr(env, AMD64Instr_SseReRg(op, zero, tmpHi));
3539 addInstr(env, AMD64Instr_SseReRg(op, zero, tmpLo));
3540 dstHi = do_sse_NotV128(env, tmpHi);
3541 dstLo = do_sse_NotV128(env, tmpLo);
3564 iselDVecExpr(&argLhi, &argLlo, env
3565 iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2);
3566 HReg dstHi = newVRegV(env);
3567 HReg dstLo = newVRegV(env);
3568 addInstr(env, mk_vMOVsd_RR(argLhi, dstHi));
3569 addInstr(env, mk_vMOVsd_RR(argLlo, dstLo));
3570 addInstr(env, AMD64Instr_Sse64Fx2(op, argRhi, dstHi));
3571 addInstr(env, AMD64Instr_Sse64Fx2(op, argRlo, dstLo));
3586 iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1);
3587 iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2);
3588 HReg dstHi = newVRegV(env);
3589 HReg dstLo = newVRegV(env);
3590 addInstr(env, mk_vMOVsd_RR(argLhi, dstHi));
3591 addInstr(env, mk_vMOVsd_RR(argLlo, dstLo));
3592 addInstr(env, AMD64Instr_Sse32Fx4(op, argRhi, dstHi));
3593 addInstr(env, AMD64Instr_Sse32Fx4(op, argRlo, dstLo));
3605 iselDVecExpr(&argLhi, &argLlo, env, e->Iex.Binop.arg1);
3606 iselDVecExpr(&argRhi, &argRlo, env, e->Iex.Binop.arg2);
3607 HReg dstHi = newVRegV(env);
3608 HReg dstLo = newVRegV(env);
3609 addInstr(env, mk_vMOVsd_RR(argLhi, dstHi));
3610 addInstr(env, mk_vMOVsd_RR(argLlo, dstLo));
3611 addInstr(env, AMD64Instr_SseReRg(op, argRhi, dstHi));
3612 addInstr(env, AMD64Instr_SseReRg(op, argRlo, dstLo));
3619 *rHi = iselVecExpr(env, e->Iex.Binop.arg1);
3620 *rLo = iselVecExpr(env, e->Iex.Binop.arg2);
3631 HReg vHi = newVRegV(env);
3632 HReg vLo = newVRegV(env);
3637 AMD64RI* q3 = iselIntExpr_RI(env, e->Iex.Qop.details->arg1);
3638 AMD64RI* q2 = iselIntExpr_RI(env, e->Iex.Qop.details->arg2);
3639 AMD64RI* q1 = iselIntExpr_RI(env, e->Iex.Qop.details->arg3);
3640 AMD64RI* q0 = iselIntExpr_RI(env, e->Iex.Qop.details->arg4);
3642 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q3, m8_rsp));
3643 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q2, m16_rsp));
3644 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vHi, m16_rsp));
3646 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q1, m8_rsp));
3647 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV, q0, m16_rsp));
3648 addInstr(env, AMD64Instr_SseLdSt(True/*load*/, 16, vLo, m16_rsp));
3656 LibVEX_ppVexHwCaps(VexArchAMD64, env->hwcaps));
3666 static void iselStmt ( ISelEnv* env, IRStmt* stmt )
3678 IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr);
3679 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data);
3686 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr);
3687 AMD64RI* ri = iselIntExpr_RI(env, stmt->Ist.Store.data);
3688 addInstr(env, AMD64Instr_Alu64M(Aalu_MOV,ri,am));
3692 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr);
3693 HReg r = iselIntExpr_R(env, stmt->Ist.Store.data);
3694 addInstr(env, AMD64Instr_Store(
3700 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr);
3701 HReg r = iselDblExpr(env, stmt->Ist.Store.data);
3702 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 8, r, am));
3706 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr);
3707 HReg r = iselFltExpr(env, stmt->Ist.Store.data);
3708 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 4, r, am));
3712 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.Store.addr);
3713 HReg r = iselVecExpr(env, stmt->Ist.Store.data);
3714 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, r, am));
3718 HReg rA = iselIntExpr_R(env, stmt->Ist.Store.addr);
3722 iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Store.data);
3723 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vLo, am0));
3724 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));
3732 IRType ty = typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
3736 AMD64RI* ri = iselIntExpr_RI(env, stmt->Ist.Put.data);
3737 addInstr(env,
3747 HReg r = iselIntExpr_R(env, stmt->Ist.Put.data);
3748 addInstr(env, AMD64Instr_Store(
3756 HReg f32 = iselFltExpr(env, stmt->Ist.Put.data);
3758 set_SSE_rounding_default(env); /* paranoia */
3759 addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 4, f32, am ));
3763 HReg f64 = iselDblExpr(env, stmt->Ist.Put.data);
3766 addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 8, f64, am ));
3770 HReg vec = iselVecExpr(env, stmt->Ist.Put.data);
3773 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vec, am));
3778 iselDVecExpr(&vHi, &vLo, env, stmt->Ist.Put.data);
3782 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vLo, am0));
3783 addInstr(env, AMD64Instr_SseLdSt(False/*store*/, 16, vHi, am16));
3795 env, puti->descr,
3798 IRType ty = typeOfIRExpr(env->type_env, puti->data);
3800 HReg val = iselDblExpr(env, puti->data);
3801 addInstr(env, AMD64Instr_SseLdSt( False/*store*/, 8, val, am ));
3805 HReg r = iselIntExpr_R(env, puti->data);
3806 addInstr(env, AMD64Instr_Store( 1, r, am ));
3810 AMD64RI* ri = iselIntExpr_RI(env, puti->data);
3811 addInstr(env, AMD64Instr_Alu64M( Aalu_MOV, ri, am ));
3820 IRType ty = typeOfIRTemp(env->type_env, tmp);
3831 AMD64AMode* am = iselIntExpr_AMode(env, stmt->Ist.WrTmp.data);
3832 HReg dst = lookupIRTemp(env, tmp);
3838 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV, AMD64RMI_Reg(src), dst));
3840 addInstr(env, AMD64Instr_Lea64(am,dst));
3847 AMD64RMI* rmi = iselIntExpr_RMI(env, stmt->Ist.WrTmp.data);
3848 HReg dst = lookupIRTemp(env, tmp);
3849 addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,rmi,dst));
3854 iselInt128Expr(&rHi,&rLo, env, stmt->Ist.WrTmp.data);
3855 lookupIRTempPair( &dstHi, &dstLo, env, tmp);
3856 addInstr(env, mk_iMOVsd_RR(rHi,dstHi) );
3857 addInstr(env, mk_iMOVsd_RR(rLo,dstLo) );
3861 AMD64CondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data);
3862 HReg dst = lookupIRTemp(env, tmp);
3863 addInstr(env, AMD64Instr_Set64(cond, dst));
3867 HReg dst = lookupIRTemp(env, tmp);
3868 HReg src = iselDblExpr(env, stmt->Ist.WrTmp.data);
3869 addInstr(env, mk_vMOVsd_RR(src, dst));
3873 HReg dst = lookupIRTemp(env, tmp);
3874 HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data);
3875 addInstr(env, mk_vMOVsd_RR(src, dst));
3879 HReg dst = lookupIRTemp(env, tmp);
3880 HReg src = iselVecExpr(env, stmt->Ist.WrTmp.data);
3881 addInstr(env, mk_vMOVsd_RR(src, dst));
3886 iselDVecExpr(&rHi,&rLo, env, stmt->Ist.WrTmp.data);
3887 lookupIRTempPair( &dstHi, &dstLo, env, tmp);
3888 addInstr(env, mk_vMOVsd_RR(rHi,dstHi) );
3889 addInstr(env, mk_vMOVsd_RR(rLo,dstLo) );
3907 doHelperCall( env, passBBP, d->guard, d->cee, d->args );
3914 retty = typeOfIRTemp(env->type_env, d->tmp);
3919 HReg dst = lookupIRTemp(env, d->tmp);
3920 addInstr(env, mk_iMOVsd_RR(hregAMD64_RAX(),dst) );
3930 addInstr(env, AMD64Instr_MFence());
3943 IRType ty = typeOfIRExpr(env->type_env, cas->dataLo);
3945 AMD64AMode* am = iselIntExpr_AMode(env, cas->addr);
3946 HReg rData = iselIntExpr_R(env, cas->dataLo);
3947 HReg rExpd = iselIntExpr_R(env, cas->expdLo);
3948 HReg rOld = lookupIRTemp(env, cas->oldLo);
3951 addInstr(env, mk_iMOVsd_RR(rExpd, rOld));
3952 addInstr(env, mk_iMOVsd_RR(rExpd, hregAMD64_RAX()));
3953 addInstr(env, mk_iMOVsd_RR(rData, hregAMD64_RBX()));
3961 addInstr(env, AMD64Instr_ACAS(am, sz));
3962 addInstr(env, AMD64Instr_CMov64(
3969 IRType ty = typeOfIRExpr(env->type_env, cas->dataLo);
3973 AMD64AMode* am = iselIntExpr_AMode(env, cas->addr);
3974 HReg rDataHi = iselIntExpr_R(env, cas->dataHi);
3975 HReg rDataLo = iselIntExpr_R(env, cas->dataLo);
3976 HReg rExpdHi = iselIntExpr_R(env, cas->expdHi);
3977 HReg rExpdLo = iselIntExpr_R(env, cas->expdLo);
3978 HReg rOldHi = lookupIRTemp(env, cas->oldHi);
3979 HReg rOldLo = lookupIRTemp(env, cas->oldLo);
3982 if (!(env->hwcaps & VEX_HWCAPS_AMD64_CX16))
3994 addInstr(env, mk_iMOVsd_RR(rExpdHi, rOldHi));
3995 addInstr(env, mk_iMOVsd_RR(rExpdLo, rOldLo));
3996 addInstr(env, mk_iMOVsd_RR(rExpdHi, hregAMD64_RDX()));
3997 addInstr(env, mk_iMOVsd_RR(rExpdLo, hregAMD64_RAX()));
3998 addInstr(env, mk_iMOVsd_RR(rDataHi, hregAMD64_RCX()));
3999 addInstr(env, mk_iMOVsd_RR(rDataLo, hregAMD64_RBX()));
4000 addInstr(env, AMD64Instr_DACAS(am, sz));
4001 addInstr(env,
4004 addInstr(env,
4032 AMD64CondCode cc = iselCondCode(env, stmt->Ist.Exit.guard);
4038 if (env->chainingAllowed) {
4043 = ((Addr64)stmt->Ist.Exit.dst->Ico.U64) > env->max_ga;
4045 addInstr(env, AMD64Instr_XDirect(stmt->Ist.Exit.dst->Ico.U64,
4051 HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
4052 addInstr(env, AMD64Instr_XAssisted(r, amRIP, cc, Ijk_Boring));
4070 HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
4071 addInstr(env, AMD64Instr_XAssisted(r, amRIP, cc, stmt->Ist.Exit.jk));
4094 static void iselNext ( ISelEnv* env,
4112 if (env->chainingAllowed) {
4117 = ((Addr64)cdst->Ico.U64) > env->max_ga;
4119 addInstr(env, AMD64Instr_XDirect(cdst->Ico.U64,
4127 HReg r = iselIntExpr_R(env, next);
4128 addInstr(env, AMD64Instr_XAssisted(r, amRIP, Acc_ALWAYS,
4138 HReg r = iselIntExpr_R(env, next);
4140 if (env->chainingAllowed) {
4141 addInstr(env, AMD64Instr_XIndir(r, amRIP, Acc_ALWAYS));
4143 addInstr(env, AMD64Instr_XAssisted(r, amRIP, Acc_ALWAYS,
4164 HReg r = iselIntExpr_R(env, next);
4166 addInstr(env, AMD64Instr_XAssisted(r, amRIP, Acc_ALWAYS, jk));
4200 ISelEnv* env;
4213 env = LibVEX_Alloc(sizeof(ISelEnv));
4214 env->vreg_ctr = 0;
4217 env->code = newHInstrArray();
4219 /* Copy BB's type env. */
4220 env->type_env = bb->tyenv;
4224 env->n_vregmap = bb->tyenv->types_used;
4225 env->vregmap = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
4226 env->vregmapHI = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
4229 env->chainingAllowed = chainingAllowed;
4230 env->hwcaps = hwcaps_host;
4231 env->max_ga = max_ga;
4236 for (i = 0; i < env->n_vregmap; i++) {
4260 env->vregmap[i] = hreg;
4261 env->vregmapHI[i] = hregHI;
4263 env->vreg_ctr = j;
4268 addInstr(env, AMD64Instr_EvCheck(amCounter, amFailAddr));
4275 addInstr(env, AMD64Instr_ProfInc());
4281 iselStmt(env, bb->stmts[i]);
4283 iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
4286 env->code->n_vregs = env->vreg_ctr;
4287 return env->code;
