Lines Matching refs:env
129 static HReg lookupIRTemp ( ISelEnv* env, IRTemp tmp )
132 vassert(tmp < env->n_vregmap);
133 return env->vregmap[tmp];
136 static void lookupIRTemp64 ( HReg* vrHI, HReg* vrLO, ISelEnv* env, IRTemp tmp )
139 vassert(tmp < env->n_vregmap);
140 vassert(env->vregmapHI[tmp] != INVALID_HREG);
141 *vrLO = env->vregmap[tmp];
142 *vrHI = env->vregmapHI[tmp];
145 static void addInstr ( ISelEnv* env, ARMInstr* instr )
147 addHInstr(env->code, instr);
162 static HReg newVRegI ( ISelEnv* env )
164 HReg reg = mkHReg(env->vreg_ctr, HRcInt32, True/*virtual reg*/);
165 env->vreg_ctr++;
169 static HReg newVRegD ( ISelEnv* env )
171 HReg reg = mkHReg(env->vreg_ctr, HRcFlt64, True/*virtual reg*/);
172 env->vreg_ctr++;
176 static HReg newVRegF ( ISelEnv* env )
178 HReg reg = mkHReg(env->vreg_ctr, HRcFlt32, True/*virtual reg*/);
179 env->vreg_ctr++;
183 static HReg newVRegV ( ISelEnv* env )
185 HReg reg = mkHReg(env->vreg_ctr, HRcVec128, True/*virtual reg*/);
186 env->vreg_ctr++;
217 static ARMAMode1* iselIntExpr_AMode1_wrk ( ISelEnv* env, IRExpr* e );
218 static ARMAMode1* iselIntExpr_AMode1 ( ISelEnv* env, IRExpr* e );
220 static ARMAMode2* iselIntExpr_AMode2_wrk ( ISelEnv* env, IRExpr* e );
221 static ARMAMode2* iselIntExpr_AMode2 ( ISelEnv* env, IRExpr* e );
223 static ARMAModeV* iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e );
224 static ARMAModeV* iselIntExpr_AModeV ( ISelEnv* env, IRExpr* e );
226 static ARMAModeN* iselIntExpr_AModeN_wrk ( ISelEnv* env, IRExpr* e );
227 static ARMAModeN* iselIntExpr_AModeN ( ISelEnv* env, IRExpr* e );
230 ( /*OUT*/Bool* didInv, Bool mayInv, ISelEnv* env, IRExpr* e );
232 ( /*OUT*/Bool* didInv, Bool mayInv, ISelEnv* env, IRExpr* e );
234 static ARMRI5* iselIntExpr_RI5_wrk ( ISelEnv* env, IRExpr* e );
235 static ARMRI5* iselIntExpr_RI5 ( ISelEnv* env, IRExpr* e );
237 static ARMCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e );
238 static ARMCondCode iselCondCode ( ISelEnv* env, IRExpr* e );
240 static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e );
241 static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e );
244 ISelEnv* env, IRExpr* e );
246 ISelEnv* env, IRExpr* e );
248 static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e );
249 static HReg iselDblExpr ( ISelEnv* env, IRExpr* e );
251 static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e );
252 static HReg iselFltExpr ( ISelEnv* env, IRExpr* e );
254 static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e );
255 static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e );
257 static HReg iselNeonExpr_wrk ( ISelEnv* env, IRExpr* e );
258 static HReg iselNeonExpr ( ISelEnv* env, IRExpr* e );
298 static void set_VFP_rounding_default ( ISelEnv* env )
303 HReg rTmp = newVRegI(env);
304 addInstr(env, ARMInstr_Imm32(rTmp, DEFAULT_FPSCR));
305 addInstr(env, ARMInstr_FPSCR(True/*toFPSCR*/, rTmp));
314 void set_VFP_rounding_mode ( ISelEnv* env, IRExpr* mode )
330 HReg irrm = iselIntExpr_R(env, mode);
331 HReg tL = newVRegI(env);
332 HReg tR = newVRegI(env);
333 HReg t3 = newVRegI(env);
342 addInstr(env, ARMInstr_Shift(ARMsh_SHL, tL, irrm, ARMRI5_I5(1)));
343 addInstr(env, ARMInstr_Shift(ARMsh_SHR, tR, irrm, ARMRI5_I5(1)));
344 addInstr(env, ARMInstr_Alu(ARMalu_AND, tL, tL, ARMRI84_I84(2,0)));
345 addInstr(env, ARMInstr_Alu(ARMalu_AND, tR, tR, ARMRI84_I84(1,0)));
346 addInstr(env, ARMInstr_Alu(ARMalu_OR, t3, tL, ARMRI84_R(tR)));
347 addInstr(env, ARMInstr_Shift(ARMsh_SHL, t3, t3, ARMRI5_I5(22)));
348 addInstr(env, ARMInstr_FPSCR(True/*toFPSCR*/, t3));
379 Bool doHelperCall ( ISelEnv* env,
488 addInstr(env, mk_iMOVds_RR( argregs[nextArgReg],
494 IRType aTy = typeOfIRExpr(env->type_env, args[i]);
498 addInstr(env, mk_iMOVds_RR( argregs[nextArgReg],
499 iselIntExpr_R(env, args[i]) ));
510 addInstr(env, ARMInstr_Imm32( argregs[nextArgReg], 0xAA ));
516 iselInt64Expr(&raHi, &raLo, env, args[i]);
517 addInstr(env, mk_iMOVds_RR( argregs[nextArgReg], raLo ));
519 addInstr(env, mk_iMOVds_RR( argregs[nextArgReg], raHi ));
537 tmpregs[nextArgReg] = newVRegI(env);
538 addInstr(env, mk_iMOVds_RR( tmpregs[nextArgReg],
544 IRType aTy = typeOfIRExpr(env->type_env, args[i]);
548 tmpregs[nextArgReg] = iselIntExpr_R(env, args[i]);
558 iselInt64Expr(&raHi, &raLo, env, args[i]);
577 cc = iselCondCode( env, guard );
584 addInstr(env, ARMInstr_Imm32( argregs[i], 0xAA ));
589 addInstr( env, mk_iMOVds_RR( argregs[i], tmpregs[i] ) );
618 addInstr(env, ARMInstr_Call( cc, target, nextArgReg ));
672 static ARMAMode1* iselIntExpr_AMode1 ( ISelEnv* env, IRExpr* e )
674 ARMAMode1* am = iselIntExpr_AMode1_wrk(env, e);
679 static ARMAMode1* iselIntExpr_AMode1_wrk ( ISelEnv* env, IRExpr* e )
681 IRType ty = typeOfIRExpr(env->type_env,e);
696 reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
704 HReg reg = iselIntExpr_R(env, e);
738 static ARMAMode2* iselIntExpr_AMode2 ( ISelEnv* env, IRExpr* e )
740 ARMAMode2* am = iselIntExpr_AMode2_wrk(env, e);
745 static ARMAMode2* iselIntExpr_AMode2_wrk ( ISelEnv* env, IRExpr* e )
747 IRType ty = typeOfIRExpr(env->type_env,e);
762 reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
770 HReg reg = iselIntExpr_R(env, e);
792 static ARMAModeV* iselIntExpr_AModeV ( ISelEnv* env, IRExpr* e )
794 ARMAModeV* am = iselIntExpr_AModeV_wrk(env, e);
799 static ARMAModeV* iselIntExpr_AModeV_wrk ( ISelEnv* env, IRExpr* e )
801 IRType ty = typeOfIRExpr(env->type_env,e);
814 reg = iselIntExpr_R(env, e->Iex.Binop.arg1);
822 HReg reg = iselIntExpr_R(env, e);
830 static ARMAModeN* iselIntExpr_AModeN ( ISelEnv* env, IRExpr* e )
832 return iselIntExpr_AModeN_wrk(env, e);
835 static ARMAModeN* iselIntExpr_AModeN_wrk ( ISelEnv* env, IRExpr* e )
837 HReg reg = iselIntExpr_R(env, e);
852 ISelEnv* env, IRExpr* e )
857 ri = iselIntExpr_RI84_wrk(didInv, mayInv, env, e);
873 ISelEnv* env, IRExpr* e )
875 IRType ty = typeOfIRExpr(env->type_env,e);
902 HReg r = iselIntExpr_R ( env, e );
912 static ARMRI5* iselIntExpr_RI5 ( ISelEnv* env, IRExpr* e )
914 ARMRI5* ri = iselIntExpr_RI5_wrk(env, e);
929 static ARMRI5* iselIntExpr_RI5_wrk ( ISelEnv* env, IRExpr* e )
931 IRType ty = typeOfIRExpr(env->type_env,e);
951 HReg r = iselIntExpr_R ( env, e );
963 static ARMCondCode iselCondCode ( ISelEnv* env, IRExpr* e )
965 ARMCondCode cc = iselCondCode_wrk(env,e);
970 static ARMCondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e )
973 vassert(typeOfIRExpr(env->type_env,e) == Ity_I1);
977 HReg rTmp = lookupIRTemp(env, e->Iex.RdTmp.tmp);
980 addInstr(env, ARMInstr_CmpOrTst(False/*test*/, rTmp, one));
987 return 1 ^ iselCondCode(env, e->Iex.Unop.arg);
994 HReg rTmp = iselIntExpr_R(env, e->Iex.Unop.arg);
996 addInstr(env, ARMInstr_CmpOrTst(False/*test*/, rTmp, one));
1004 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg);
1006 addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r1, xFF));
1014 HReg r1 = iselIntExpr_R(env, e->Iex.Unop.arg);
1016 addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, r1, zero));
1025 HReg tmp = newVRegI(env);
1027 iselInt64Expr(&tHi, &tLo, env, e->Iex.Unop.arg);
1028 addInstr(env, ARMInstr_Alu(ARMalu_OR, tmp, tHi, ARMRI84_R(tLo)));
1029 addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, tmp, zero));
1041 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1043 env, e->Iex.Binop.arg2);
1044 addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, argL, argR));
1073 static HReg iselIntExpr_R ( ISelEnv* env, IRExpr* e )
1075 HReg r = iselIntExpr_R_wrk(env, e);
1086 static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
1088 IRType ty = typeOfIRExpr(env->type_env,e);
1096 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
1101 HReg dst = newVRegI(env);
1107 ARMAMode1* amode = iselIntExpr_AMode1 ( env, e->Iex.Load.addr );
1108 addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, dst, amode));
1112 ARMAMode2* amode = iselIntExpr_AMode2 ( env, e->Iex.Load.addr );
1113 addInstr(env, ARMInstr_LdSt16(True/*isLoad*/, False/*!signedLoad*/,
1118 ARMAMode1* amode = iselIntExpr_AMode1 ( env, e->Iex.Load.addr );
1119 addInstr(env, ARMInstr_LdSt8U(True/*isLoad*/, dst, amode));
1124 //zz addInstr(env, X86Instr_LoadEX(2,False,amode,dst));
1128 //zz addInstr(env, X86Instr_LoadEX(1,False,amode,dst));
1141 //zz HReg junk = newVRegF(env);
1142 //zz HReg dst = newVRegI(env);
1143 //zz HReg srcL = iselDblExpr(env, triop->arg2);
1144 //zz HReg srcR = iselDblExpr(env, triop->arg3);
1147 //zz addInstr(env, X86Instr_FpBinary(
1154 //zz addInstr(env, X86Instr_FpStSW_AX());
1155 //zz addInstr(env, mk_iMOVsd_RR(hregX86_EAX(), dst));
1156 //zz addInstr(env, X86Instr_Alu32R(Xalu_AND, X86RMI_Imm(0x4700), dst));
1173 HReg dst = newVRegI(env);
1174 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1176 env, e->Iex.Binop.arg2);
1177 addInstr(env, ARMInstr_Alu(didInv ? ARMalu_BIC : ARMalu_AND,
1186 HReg dst = newVRegI(env);
1187 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1189 env, e->Iex.Binop.arg2);
1190 addInstr(env, ARMInstr_Alu(aop, dst, argL, argR));
1198 HReg dst = newVRegI(env);
1199 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1200 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1202 addInstr(env,
1215 HReg dst = newVRegI(env);
1216 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1217 ARMRI5* argR = iselIntExpr_RI5(env, e->Iex.Binop.arg2);
1218 addInstr(env, ARMInstr_Shift(sop, dst, argL, argR));
1227 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1228 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1229 HReg dst = newVRegI(env);
1230 addInstr(env, mk_iMOVds_RR(hregARM_R2(), argL));
1231 addInstr(env, mk_iMOVds_RR(hregARM_R3(), argR));
1232 addInstr(env, ARMInstr_Mul(ARMmul_PLAIN));
1233 addInstr(env, mk_iMOVds_RR(dst, hregARM_R0()));
1240 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1241 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1242 HReg dst = newVRegI(env);
1243 addInstr(env, ARMInstr_CmpOrTst(True/*isCmp*/, argL,
1245 addInstr(env, mk_iMOVds_RR(dst, argL));
1246 addInstr(env, ARMInstr_CMov(ARMcc_LO, dst, ARMRI84_R(argR)));
1251 HReg dL = iselDblExpr(env, e->Iex.Binop.arg1);
1252 HReg dR = iselDblExpr(env, e->Iex.Binop.arg2);
1253 HReg dst = newVRegI(env);
1256 addInstr(env, ARMInstr_VCmpD(dL, dR));
1258 addInstr(env, ARMInstr_Imm32(dst, 0));
1259 addInstr(env, ARMInstr_CMov(ARMcc_EQ, dst, ARMRI84_I84(0x40,0))); //EQ
1260 addInstr(env, ARMInstr_CMov(ARMcc_MI, dst, ARMRI84_I84(0x01,0))); //LT
1261 addInstr(env, ARMInstr_CMov(ARMcc_GT, dst, ARMRI84_I84(0x00,0))); //GT
1262 addInstr(env, ARMInstr_CMov(ARMcc_VS, dst, ARMRI84_I84(0x45,0))); //UN
1274 HReg valD = iselDblExpr(env, e->Iex.Binop.arg2);
1275 set_VFP_rounding_mode(env, e->Iex.Binop.arg1);
1277 HReg valF = newVRegF(env);
1278 addInstr(env, ARMInstr_VCvtID(False/*!iToD*/, syned,
1280 set_VFP_rounding_default(env);
1282 HReg dst = newVRegI(env);
1283 addInstr(env, ARMInstr_VXferS(False/*!toS*/, valF, dst));
1290 HReg res = newVRegI(env);
1291 HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1);
1294 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
1305 addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS,
1315 HReg res = newVRegI(env);
1316 HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1);
1319 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
1330 addInstr(env, ARMInstr_NUnaryS(ARMneon_GETELEMS,
1389 HReg regL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1390 HReg regR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1391 HReg res = newVRegI(env);
1392 addInstr(env, mk_iMOVds_RR(hregARM_R0(), regL));
1393 addInstr(env, mk_iMOVds_RR(hregARM_R1(), regR));
1394 addInstr(env, ARMInstr_Call( ARMcc_AL, (HWord)Ptr_to_ULong(fn), 2 ));
1395 addInstr(env, mk_iMOVds_RR(res, hregARM_R0()));
1412 //zz HReg dst = newVRegI(env);
1413 //zz HReg src = iselIntExpr_R(env, expr32);
1414 //zz addInstr(env, mk_iMOVsd_RR(src,dst) );
1415 //zz addInstr(env, X86Instr_Alu32R(Xalu_AND,
1428 //zz HReg dst = newVRegI(env);
1429 //zz X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] );
1430 //zz addInstr(env, X86Instr_LoadEX(1,False,amode,dst));
1442 //zz HReg dst = newVRegI(env);
1443 //zz X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] );
1444 //zz addInstr(env, X86Instr_LoadEX(1,True,amode,dst));
1456 //zz HReg dst = newVRegI(env);
1457 //zz X86AMode* amode = iselIntExpr_AMode ( env, mi.bindee[0] );
1458 //zz addInstr(env, X86Instr_LoadEX(2,False,amode,dst));
1469 //zz dst = newVRegI(env);
1472 //zz addInstr(env, X86Instr_LoadEX(1,False,amode,dst));
1483 //zz dst = newVRegI(env);
1486 //zz addInstr(env, X86Instr_LoadEX(2,False,amode,dst));
1493 HReg dst = newVRegI(env);
1494 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1495 addInstr(env, ARMInstr_Alu(ARMalu_AND,
1502 //zz HReg dst = newVRegI(env);
1503 //zz HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1505 //zz addInstr(env, mk_iMOVsd_RR(src,dst) );
1506 //zz addInstr(env, X86Instr_Alu32R(Xalu_AND,
1513 HReg dst = newVRegI(env);
1514 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1516 addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, src, amt));
1517 addInstr(env, ARMInstr_Shift(ARMsh_SHR, dst, dst, amt));
1522 HReg dst = newVRegI(env);
1523 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1525 addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, src, amt));
1526 addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt));
1532 HReg dst = newVRegI(env);
1533 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1534 addInstr(env, ARMInstr_Unary(ARMun_NOT, dst, src));
1539 iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
1544 iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
1549 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
1550 HReg tHi = newVRegI(env);
1551 HReg tLo = newVRegI(env);
1552 HReg tmp = iselNeon64Expr(env, e->Iex.Unop.arg);
1553 addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
1557 iselInt64Expr(&rHi,&rLo, env, e->Iex.Unop.arg);
1563 //zz HReg dst = newVRegI(env);
1564 //zz HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1566 //zz addInstr(env, mk_iMOVsd_RR(src,dst) );
1567 //zz addInstr(env, X86Instr_Sh32(Xsh_SHR, shift, dst));
1572 HReg dst = newVRegI(env);
1573 ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg);
1574 addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0)));
1575 addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0)));
1580 HReg dst = newVRegI(env);
1581 ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg);
1586 addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0)));
1587 addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0)));
1588 addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt));
1589 addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt));
1598 //zz HReg dst = newVRegI(env);
1599 //zz X86CondCode cond = iselCondCode(env, e->Iex.Unop.arg);
1600 //zz addInstr(env, X86Instr_Set32(cond,dst));
1601 //zz addInstr(env, X86Instr_Sh32(Xsh_SHL, 31, dst));
1602 //zz addInstr(env, X86Instr_Sh32(Xsh_SAR, 31, dst));
1607 //zz HReg dst = newVRegI(env);
1608 //zz HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1609 //zz addInstr(env, X86Instr_Bsfr32(True,src,dst));
1614 HReg dst = newVRegI(env);
1615 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1616 addInstr(env, ARMInstr_Unary(ARMun_CLZ, dst, src));
1621 HReg dst = newVRegI(env);
1622 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1623 addInstr(env, ARMInstr_Unary(ARMun_NEG, dst, src));
1624 addInstr(env, ARMInstr_Alu(ARMalu_OR, dst, dst, ARMRI84_R(src)));
1625 addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, ARMRI5_I5(31)));
1630 HReg dst = newVRegI(env);
1631 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
1632 addInstr(env, ARMInstr_Unary(ARMun_NEG, dst, src));
1633 addInstr(env, ARMInstr_Alu(ARMalu_OR, dst, dst, ARMRI84_R(src)));
1638 //zz HReg dst = newVRegI(env);
1639 //zz HReg vec = iselVecExpr(env, e->Iex.Unop.arg);
1641 //zz sub_from_esp(env, 16);
1642 //zz addInstr(env, X86Instr_SseLdSt(False/*store*/, vec, esp0));
1643 //zz addInstr(env, X86Instr_Alu32R( Xalu_MOV, X86RMI_Mem(esp0), dst ));
1644 //zz add_to_esp(env, 16);
1649 HReg dst = newVRegI(env);
1650 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
1651 addInstr(env, ARMInstr_VXferS(False/*!toS*/, src, dst));
1660 return iselIntExpr_R(env, e->Iex.Unop.arg);
1678 HReg arg = iselIntExpr_R(env, e->Iex.Unop.arg);
1679 HReg res = newVRegI(env);
1680 addInstr(env, mk_iMOVds_RR(hregARM_R0(), arg));
1681 addInstr(env, ARMInstr_Call( ARMcc_AL, (HWord)Ptr_to_ULong(fn), 1 ));
1682 addInstr(env, mk_iMOVds_RR(res, hregARM_R0()));
1694 HReg dst = newVRegI(env);
1695 addInstr(env, ARMInstr_LdSt32(
1702 //zz HReg dst = newVRegI(env);
1703 //zz addInstr(env, X86Instr_LoadEX(
1716 //zz env, e->Iex.GetI.descr,
1718 //zz HReg dst = newVRegI(env);
1720 //zz addInstr(env, X86Instr_LoadEX( 1, False, am, dst ));
1724 //zz addInstr(env, X86Instr_Alu32R(Xalu_MOV, X86RMI_Mem(am), dst));
1732 HReg dst = newVRegI(env);
1741 Bool ok = doHelperCall( env, False,
1744 addInstr(env, mk_iMOVds_RR(dst, hregARM_R0()));
1754 HReg dst = newVRegI(env);
1761 addInstr(env, ARMInstr_Imm32(dst, u));
1776 HReg rX = iselIntExpr_R(env, e->Iex.Mux0X.exprX);
1777 ARMRI84* r0 = iselIntExpr_RI84(NULL, False, env, e->Iex.Mux0X.expr0);
1778 HReg dst = newVRegI(env);
1779 addInstr(env, mk_iMOVds_RR(dst, rX));
1780 cc = iselCondCode(env, cond->Iex.Unop.arg->Iex.Unop.arg);
1781 addInstr(env, ARMInstr_CMov(cc ^ 1, dst, r0));
1788 HReg rX = iselIntExpr_R(env, e->Iex.Mux0X.exprX);
1789 ARMRI84* r0 = iselIntExpr_RI84(NULL, False, env, e->Iex.Mux0X.expr0);
1790 HReg dst = newVRegI(env);
1791 addInstr(env, mk_iMOVds_RR(dst, rX));
1792 r8 = iselIntExpr_R(env, cond);
1793 addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8,
1795 addInstr(env, ARMInstr_CMov(ARMcc_EQ, dst, r0));
1819 static void iselInt64Expr ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
1821 iselInt64Expr_wrk(rHi, rLo, env, e);
1832 static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo, ISelEnv* env, IRExpr* e )
1835 vassert(typeOfIRExpr(env->type_env,e) == Ity_I64);
1842 HReg tHi = newVRegI(env);
1843 HReg tLo = newVRegI(env);
1845 addInstr(env, ARMInstr_Imm32(tHi, wHi));
1846 addInstr(env, ARMInstr_Imm32(tLo, wLo));
1854 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
1855 HReg tHi = newVRegI(env
1856 HReg tLo = newVRegI(env);
1857 HReg tmp = iselNeon64Expr(env, e);
1858 addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
1862 lookupIRTemp64( rHi, rLo, env, e->Iex.RdTmp.tmp);
1871 rA = iselIntExpr_R(env, e->Iex.Load.addr);
1872 tHi = newVRegI(env);
1873 tLo = newVRegI(env);
1874 addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tHi, ARMAMode1_RI(rA, 4)));
1875 addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tLo, ARMAMode1_RI(rA, 0)));
1885 HReg tHi = newVRegI(env);
1886 HReg tLo = newVRegI(env);
1887 addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tHi, am4));
1888 addInstr(env, ARMInstr_LdSt32(True/*isLoad*/, tLo, am0));
1901 HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);
1902 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1903 HReg tHi = newVRegI(env);
1904 HReg tLo = newVRegI(env);
1907 addInstr(env, mk_iMOVds_RR(hregARM_R2(), argL));
1908 addInstr(env, mk_iMOVds_RR(hregARM_R3(), argR));
1909 addInstr(env, ARMInstr_Mul(mop));
1910 addInstr(env, mk_iMOVds_RR(tHi, hregARM_R1()));
1911 addInstr(env, mk_iMOVds_RR(tLo, hregARM_R0()));
1919 HReg tHi = newVRegI(env);
1920 HReg tLo = newVRegI(env);
1921 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
1922 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
1923 addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, xHi, ARMRI84_R(yHi)));
1924 addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, xLo, ARMRI84_R(yLo)));
1932 HReg tHi = newVRegI(env);
1933 HReg tLo = newVRegI(env);
1934 iselInt64Expr(&xHi, &xLo, env, e->Iex.Binop.arg1);
1935 iselInt64Expr(&yHi, &yLo, env, e->Iex.Binop.arg2);
1936 addInstr(env, ARMInstr_Alu(ARMalu_ADDS, tLo, xLo, ARMRI84_R(yLo)));
1937 addInstr(env, ARMInstr_Alu(ARMalu_ADC, tHi, xHi, ARMRI84_R(yHi)));
1945 *rHi = iselIntExpr_R(env, e->Iex.Binop.arg1);
1946 *rLo = iselIntExpr_R(env, e->Iex.Binop.arg2);
1961 HReg dstHi = newVRegI(env);
1962 HReg dstLo = newVRegI(env);
1963 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
1964 addInstr(env, ARMInstr_VXferD(False/*!toD*/, src, dstHi, dstLo));
1973 HReg tHi = newVRegI(env);
1974 HReg tLo = newVRegI(env);
1975 HReg zero = newVRegI(env);
1977 iselInt64Expr(&yHi, &yLo, env, e->Iex.Unop.arg);
1979 addInstr(env, ARMInstr_Imm32(zero, 0));
1981 addInstr(env, ARMInstr_Alu(ARMalu_SUBS,
1984 addInstr(env, ARMInstr_Alu(ARMalu_SBC,
1989 addInstr(env, ARMInstr_Alu(ARMalu_OR, tHi, tHi, ARMRI84_R(yHi)));
1990 addInstr(env, ARMInstr_Alu(ARMalu_OR, tLo, tLo, ARMRI84_R(yLo)));
1999 HReg tmp1 = newVRegI(env);
2000 HReg tmp2 = newVRegI(env);
2002 iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg);
2004 addInstr(env, ARMInstr_Alu(ARMalu_OR,
2007 addInstr(env, ARMInstr_Unary(ARMun_NEG, tmp2, tmp1));
2008 addInstr(env, ARMInstr_Alu(ARMalu_OR,
2010 addInstr(env, ARMInstr_Shift(ARMsh_SAR,
2018 HReg dst = newVRegI(env);
2019 ARMCondCode cond = iselCondCode(env, e->Iex.Unop.arg);
2024 addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0)));
2025 addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0)));
2026 addInstr(env, ARMInstr_Shift(ARMsh_SHL, dst, dst, amt));
2027 addInstr(env, ARMInstr_Shift(ARMsh_SAR, dst, dst, amt));
2042 ty8 = typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond);
2044 iselInt64Expr(&rXhi, &rXlo, env, e->Iex.Mux0X.exprX);
2045 iselInt64Expr(&r0hi, &r0lo, env, e->Iex.Mux0X.expr0);
2046 dstHi = newVRegI(env);
2047 dstLo = newVRegI(env);
2048 addInstr(env, mk_iMOVds_RR(dstHi, rXhi));
2049 addInstr(env, mk_iMOVds_RR(dstLo, rXlo));
2050 r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
2051 addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8,
2053 addInstr(env, ARMInstr_CMov(ARMcc_EQ, dstHi, ARMRI84_R(r0hi)));
2054 addInstr(env, ARMInstr_CMov(ARMcc_EQ, dstLo, ARMRI84_R(r0lo)));
2063 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
2064 HReg tHi = newVRegI(env);
2065 HReg tLo = newVRegI(env);
2066 HReg tmp = iselNeon64Expr(env, e);
2067 addInstr(env, ARMInstr_VXferD(False, tmp, tHi, tLo));
2082 static HReg iselNeon64Expr ( ISelEnv* env, IRExpr* e )
2084 HReg r = iselNeon64Expr_wrk( env, e );
2091 static HReg iselNeon64Expr_wrk ( ISelEnv* env, IRExpr* e )
2093 IRType ty = typeOfIRExpr(env->type_env, e);
2099 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
2104 HReg res = newVRegD(env);
2105 iselInt64Expr(&rHi, &rLo, env, e);
2106 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
2112 HReg res = newVRegD(env);
2113 ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr);
2115 addInstr(env, ARMInstr_NLdStD(True, res, am));
2121 HReg addr = newVRegI(env);
2122 HReg res = newVRegD(env);
2124 addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), e->Iex.Get.offset));
2125 addInstr(env, ARMInstr_NLdStD(True, res, mkARMAModeN_R(addr)));
2137 HReg res = newVRegD(env);
2138 iselInt64Expr(&rHi, &rLo, env, e);
2139 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
2144 HReg res = newVRegD(env);
2145 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2146 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2147 addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
2152 HReg res = newVRegD(env);
2153 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2154 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2155 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
2160 HReg res = newVRegD(env);
2161 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2162 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2163 addInstr(env, ARMInstr_NBinary(ARMneon_VXOR,
2170 HReg rHi = iselIntExpr_R(env, e->Iex.Binop.arg1);
2171 HReg rLo = iselIntExpr_R(env, e->Iex.Binop.arg2);
2172 HReg res = newVRegD(env);
2173 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
2181 HReg res = newVRegD(env);
2182 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2183 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2192 addInstr(env, ARMInstr_NBinary(ARMneon_VADD,
2197 HReg res = newVRegD(env);
2198 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2199 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2201 addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP,
2206 HReg res = newVRegD(env);
2207 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2208 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2210 addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS,
2215 HReg res = newVRegD(env);
2216 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2217 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2219 addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS,
2229 HReg tmp = newVRegD(env);
2230 HReg res = newVRegD(env);
2231 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2232 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2245 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
2247 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
2249 addInstr(env, ARMInstr_NDual(ARMneon_TRN,
2252 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
2254 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
2256 addInstr(env, ARMInstr_NDual(ARMneon_TRN,
2265 HReg tmp = newVRegD(env);
2266 HReg res = newVRegD(env);
2267 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2268 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2279 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
2281 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
2283 addInstr(env, ARMInstr_NDual(ARMneon_ZIP,
2286 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
2288 env, ARMInstr_NUnary(ARMneon_COPY,
2290 addInstr(env, ARMInstr_NDual(ARMneon_ZIP,
2299 HReg tmp = newVRegD(env);
2300 HReg res = newVRegD(env);
2301 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2302 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2313 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
2315 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
2317 addInstr(env, ARMInstr_NDual(ARMneon_UZP,
2320 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
2322 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
2324 addInstr(env, ARMInstr_NDual(ARMneon_UZP,
2333 HReg res = newVRegD(env);
2334 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2335 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2344 addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU,
2352 HReg res = newVRegD(env);
2353 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2354 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2363 addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS,
2371 HReg res = newVRegD(env);
2372 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2373 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2382 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
2387 HReg res = newVRegD(env);
2388 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2389 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2391 addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP,
2399 HReg res = newVRegD(env);
2400 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2401 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2410 addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU,
2418 HReg res = newVRegD(env);
2419 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2420 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2429 addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS,
2436 HReg res = newVRegD(env);
2437 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2438 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2446 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU,
2453 HReg res = newVRegD(env);
2454 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2455 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2463 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS,
2470 HReg res = newVRegD(env);
2471 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2472 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2480 addInstr(env, ARMInstr_NBinary(ARMneon_VMINU,
2487 HReg res = newVRegD(env);
2488 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2489 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2497 addInstr(env, ARMInstr_NBinary(ARMneon_VMINS,
2504 HReg res = newVRegD(env);
2505 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2506 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2507 HReg argR2 = newVRegD(env);
2508 HReg zero = newVRegD(env);
2517 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
2518 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
2520 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
2528 HReg res = newVRegD(env);
2529 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2530 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2539 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
2546 HReg res = newVRegD(env);
2547 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2548 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2549 HReg argR2 = newVRegD(env);
2550 HReg zero = newVRegD(env);
2558 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
2559 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
2561 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
2568 HReg res = newVRegD(env);
2569 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2570 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2578 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
2586 HReg res = newVRegD(env);
2587 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2588 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2597 addInstr(env, ARMInstr_NShift(ARMneon_VQSHL,
2605 HReg res = newVRegD(env);
2606 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2607 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2616 addInstr(env, ARMInstr_NShift(ARMneon_VQSAL,
2624 HReg res = newVRegD(env);
2625 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2628 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
2640 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU,
2648 HReg res = newVRegD(env);
2649 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2652 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
2664 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS,
2672 HReg res = newVRegD(env);
2673 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2676 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
2688 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS,
2696 HReg res = newVRegD(env);
2697 HReg tmp = newVRegD(env);
2698 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2699 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
2700 HReg argR2 = newVRegI(env);
2709 addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
2710 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False));
2711 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
2719 HReg res = newVRegD(env);
2720 HReg tmp = newVRegD(env);
2721 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2722 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
2731 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR, 0, False));
2732 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
2740 HReg res = newVRegD(env);
2741 HReg tmp = newVRegD(env);
2742 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2743 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
2744 HReg argR2 = newVRegI(env);
2753 addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
2754 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, False));
2755 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
2762 HReg res = newVRegD(env);
2763 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2764 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2772 addInstr(env, ARMInstr_NBinary(ARMneon_VCGTU,
2779 HReg res = newVRegD(env);
2780 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2781 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2789 addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS,
2796 HReg res = newVRegD(env);
2797 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2798 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2806 addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ,
2813 HReg res = newVRegD(env);
2814 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2815 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2823 addInstr(env, ARMInstr_NBinary(ARMneon_VMUL,
2828 HReg res = newVRegD(env);
2829 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2830 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2832 addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP,
2838 HReg res = newVRegD(env);
2839 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2840 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2847 addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH,
2854 HReg res = newVRegD(env);
2855 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2856 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2863 addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH,
2871 HReg res = newVRegD(env);
2872 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2873 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2881 addInstr(env, ARMInstr_NBinary(ARMneon_VPADD,
2886 HReg res = newVRegD(env);
2887 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2888 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2890 addInstr(env, ARMInstr_NBinary(ARMneon_VPADDFP,
2897 HReg res = newVRegD(env);
2898 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2899 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2907 addInstr(env, ARMInstr_NBinary(ARMneon_VPMINU,
2914 HReg res = newVRegD(env);
2915 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2916 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2924 addInstr(env, ARMInstr_NBinary(ARMneon_VPMINS,
2931 HReg res = newVRegD(env);
2932 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2933 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2941 addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXU,
2948 HReg res = newVRegD(env);
2949 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2950 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2958 addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXS,
2963 HReg res = newVRegD(env);
2964 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2965 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2966 addInstr(env, ARMInstr_NBinary(ARMneon_VTBL,
2971 HReg res = newVRegD(env);
2972 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2973 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2975 addInstr(env, ARMInstr_NBinary(ARMneon_VMULP,
2980 HReg res = newVRegD(env);
2981 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2982 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2983 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF,
2988 HReg res = newVRegD(env);
2989 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2990 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2991 addInstr(env, ARMInstr_NBinary(ARMneon_VMINF,
2996 HReg res = newVRegD(env);
2997 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
2998 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
2999 addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF,
3004 HReg res = newVRegD(env);
3005 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3006 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3007 addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF,
3012 HReg res = newVRegD(env);
3013 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3014 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3015 addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF,
3020 HReg res = newVRegD(env);
3021 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3022 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3023 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF,
3028 HReg res = newVRegD(env);
3029 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3030 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
3031 addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF,
3039 HReg res = newVRegD(env);
3040 HReg arg = iselNeon64Expr(env, e->Iex.Binop.arg1);
3044 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
3058 addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, False));
3066 env);
3067 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3072 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
3087 addInstr(env, ARMInstr_NUnary(ARMneon_VDUP,
3109 HReg res = newVRegD(env);
3110 iselInt64Expr(&rHi, &rLo, env, e);
3111 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
3143 HReg res = newVRegD(env);
3144 HReg arg = iselNeon64Expr(env, mi.bindee[0]);
3145 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, False));
3148 HReg res = newVRegD(env);
3149 HReg arg = iselNeon64Expr(env, mi.bindee[0]);
3150 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, False));
3153 HReg res = newVRegD(env);
3154 HReg arg = iselNeon64Expr(env, mi.bindee[0]);
3155 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, False));
3158 HReg res = newVRegD(env);
3159 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3160 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3161 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3165 HReg res = newVRegD(env);
3166 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3167 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3168 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3172 HReg res = newVRegD(env);
3173 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3174 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3175 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3179 HReg res = newVRegD(env);
3180 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3181 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3182 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3186 HReg res = newVRegD(env);
3187 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3188 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3189 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3193 HReg res = newVRegD(env);
3194 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3195 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3196 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3200 HReg res = newVRegD(env);
3201 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3202 addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, False));
3224 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
3228 res = newVRegD(env);
3229 arg = iselNeon64Expr(env, mi.bindee[0]);
3230 addInstr(env, ARMInstr_NUnaryS(
3243 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
3247 res = newVRegD(env);
3248 arg = iselNeon64Expr(env, mi.bindee[0]);
3249 addInstr(env, ARMInstr_NUnaryS(
3262 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
3266 res = newVRegD(env);
3267 arg = iselNeon64Expr(env, mi.bindee[0]);
3268 addInstr(env, ARMInstr_NUnaryS(
3278 arg = iselIntExpr_R(env, e->Iex.Unop.arg);
3279 res = newVRegD(env);
3286 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, False));
3292 HReg res = newVRegD(env);
3293 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3301 addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, False));
3307 HReg res = newVRegD(env);
3308 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3316 addInstr(env, ARMInstr_NUnary(ARMneon_REV64,
3322 HReg res = newVRegD(env);
3323 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3330 addInstr(env, ARMInstr_NUnary(ARMneon_REV32,
3335 HReg res = newVRegD(env);
3336 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3338 addInstr(env, ARMInstr_NUnary(ARMneon_REV16,
3343 HReg x_lsh = newVRegD(env);
3344 HReg x_rsh = newVRegD(env);
3345 HReg lsh_amt = newVRegD(env);
3346 HReg rsh_amt = newVRegD(env);
3347 HReg zero = newVRegD(env);
3348 HReg tmp = newVRegD(env);
3349 HReg tmp2 = newVRegD(env);
3350 HReg res = newVRegD(env);
3351 HReg x = newVRegD(env);
3352 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3353 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, False));
3354 addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, False));
3355 addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32)));
3356 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0)));
3357 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
3359 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
3361 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
3363 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
3365 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
3372 HReg res = newVRegD(env);
3373 HReg tmp = newVRegD(env);
3374 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3382 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, False));
3383 addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, False));
3389 HReg res = newVRegD(env);
3390 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3398 addInstr(env, ARMInstr_NUnary(ARMneon_COPYN,
3405 HReg res = newVRegD(env);
3406 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3414 addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNSS,
3421 HReg res = newVRegD(env);
3422 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3430 addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUS,
3437 HReg res = newVRegD(env);
3438 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3446 addInstr(env, ARMInstr_NUnary(ARMneon_COPYQNUU,
3453 HReg res = newVRegD(env);
3454 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3462 addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS,
3469 HReg res = newVRegD(env);
3470 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3478 addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU,
3483 HReg res = newVRegD(env);
3484 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3486 addInstr(env, ARMInstr_NUnary(ARMneon_CNT,
3493 HReg res = newVRegD(env);
3494 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3502 addInstr(env, ARMInstr_NUnary(ARMneon_CLZ,
3509 HReg res = newVRegD(env);
3510 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3518 addInstr(env, ARMInstr_NUnary(ARMneon_CLS,
3523 HReg res = newVRegD(env);
3524 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3525 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS,
3530 HReg res = newVRegD(env);
3531 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3532 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU,
3537 HReg res = newVRegD(env);
3538 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3539 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF,
3544 HReg res = newVRegD(env);
3545 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3546 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF,
3551 HReg res = newVRegD(env);
3552 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3553 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF32toF16,
3558 HReg res = newVRegD(env);
3559 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3560 addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF,
3565 HReg res = newVRegD(env);
3566 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
3567 addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP,
3579 HReg res = newVRegD(env);
3580 HReg argL = iselNeon64Expr(env, mi.bindee[0]);
3581 HReg argR = iselNeon64Expr(env, mi.bindee[1]);
3582 addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP,
3586 HReg res = newVRegD(env);
3587 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3588 addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP,
3594 HReg res = newVRegD(env);
3595 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3596 addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP,
3601 HReg res = newVRegD(env);
3602 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3603 addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE,
3608 HReg res = newVRegD(env);
3609 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
3610 addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF,
3624 HReg res = newVRegD(env);
3625 HReg argL = iselNeon64Expr(env, triop->arg1);
3626 HReg argR = iselNeon64Expr(env, triop->arg2);
3629 typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) {
3638 addInstr(env, ARMInstr_NBinary(ARMneon_VEXT,
3645 HReg res = newVRegD(env);
3646 HReg dreg = iselNeon64Expr(env, triop->arg1);
3647 HReg arg = iselIntExpr_R(env, triop->arg3);
3650 typeOfIRExpr(env->type_env, triop->arg2) != Ity_I8) {
3661 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, res, dreg, 4, False));
3662 addInstr(env, ARMInstr_NUnaryS(ARMneon_SETELEM,
3676 HReg res = newVRegD(env);
3677 iselInt64Expr(&rHi, &rLo, env, e);
3678 addInstr(env, ARMInstr_VXferD(True/*toD*/, res, rHi, rLo));
3686 static HReg iselNeonExpr ( ISelEnv* env, IRExpr* e )
3688 HReg r = iselNeonExpr_wrk( env, e );
3695 static HReg iselNeonExpr_wrk ( ISelEnv* env, IRExpr* e )
3697 IRType ty = typeOfIRExpr(env->type_env, e);
3703 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
3712 HReg res = newVRegV(env);
3713 addInstr(env, ARMInstr_NeonImm(res, ARMNImm_TI(0, 0)));
3721 HReg res = newVRegV(env);
3722 ARMAModeN* am = iselIntExpr_AModeN(env, e->Iex.Load.addr);
3724 addInstr(env, ARMInstr_NLdStQ(True, res, am));
3729 HReg addr = newVRegI(env);
3730 HReg res = newVRegV(env);
3732 addInstr(env, ARMInstr_Add32(addr, hregARM_R8(), e->Iex.Get.offset));
3733 addInstr(env, ARMInstr_NLdStQ(True, res, mkARMAModeN_R(addr)));
3768 HReg res = newVRegV(env);
3769 HReg arg = iselNeonExpr(env, mi.bindee[0]);
3770 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 0, True));
3773 HReg res = newVRegV(env);
3774 HReg arg = iselNeonExpr(env, mi.bindee[0]);
3775 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 1, True));
3778 HReg res = newVRegV(env);
3779 HReg arg = iselNeonExpr(env, mi.bindee[0]);
3780 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, res, arg, 2, True));
3783 HReg res = newVRegV(env);
3784 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3785 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3786 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3790 HReg res = newVRegV(env);
3791 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3792 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3793 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3797 HReg res = newVRegV(env);
3798 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3799 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3800 addInstr(env, ARMInstr_NBinary(ARMneon_VCGES,
3804 HReg res = newVRegV(env);
3805 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3806 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3807 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3811 HReg res = newVRegV(env);
3812 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3813 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3814 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3818 HReg res = newVRegV(env);
3819 HReg argL = iselNeonExpr(env, mi.bindee[0]);
3820 HReg argR = iselNeonExpr(env, mi.bindee[1]);
3821 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEU,
3825 HReg res = newVRegV(env);
3826 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3827 env, ARMInstr_NUnary(ARMneon_NOT, res, arg, 4, True));
3849 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
3853 res = newVRegV(env);
3854 arg = iselNeon64Expr(env, mi.bindee[0]);
3855 addInstr(env, ARMInstr_NUnaryS(
3868 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
3872 res = newVRegV(env);
3873 arg = iselNeon64Expr(env, mi.bindee[0]);
3874 addInstr(env, ARMInstr_NUnaryS(
3887 typeOfIRExpr(env->type_env, mi.bindee[1]) == Ity_I8) {
3891 res = newVRegV(env);
3892 arg = iselNeon64Expr(env, mi.bindee[0]);
3893 addInstr(env, ARMInstr_NUnaryS(
3903 arg = iselIntExpr_R(env, e->Iex.Unop.arg);
3904 res = newVRegV(env);
3911 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, res, arg, size, True));
3917 HReg res = newVRegV(env);
3918 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3926 addInstr(env, ARMInstr_NUnary(ARMneon_ABS, res, arg, size, True));
3932 HReg res = newVRegV(env);
3933 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3941 addInstr(env, ARMInstr_NUnary(ARMneon_REV64,
3947 HReg res = newVRegV(env);
3948 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3955 addInstr(env, ARMInstr_NUnary(ARMneon_REV32,
3960 HReg res = newVRegV(env);
3961 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3963 addInstr(env, ARMInstr_NUnary(ARMneon_REV16,
3968 HReg x_lsh = newVRegV(env);
3969 HReg x_rsh = newVRegV(env);
3970 HReg lsh_amt = newVRegV(env);
3971 HReg rsh_amt = newVRegV(env);
3972 HReg zero = newVRegV(env);
3973 HReg tmp = newVRegV(env);
3974 HReg tmp2 = newVRegV(env);
3975 HReg res = newVRegV(env);
3976 HReg x = newVRegV(env);
3977 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
3978 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp2, arg, 2, True));
3979 addInstr(env, ARMInstr_NUnary(ARMneon_NOT, x, tmp2, 4, True));
3980 addInstr(env, ARMInstr_NeonImm(lsh_amt, ARMNImm_TI(0, 32)));
3981 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0, 0)));
3982 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
3984 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
3986 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
3988 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
3990 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
3997 HReg res = newVRegV(env);
3998 HReg tmp = newVRegV(env);
3999 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4007 addInstr(env, ARMInstr_NUnary(ARMneon_EQZ, tmp, arg, size, True));
4008 addInstr(env, ARMInstr_NUnary(ARMneon_NOT, res, tmp, 4, True));
4014 HReg res = newVRegV(env);
4015 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
4023 addInstr(env, ARMInstr_NUnary(ARMneon_COPYLU,
4030 HReg res = newVRegV(env);
4031 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
4039 addInstr(env, ARMInstr_NUnary(ARMneon_COPYLS,
4046 HReg res = newVRegV(env);
4047 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4055 addInstr(env, ARMInstr_NUnary(ARMneon_PADDLS,
4062 HReg res = newVRegV(env);
4063 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4071 addInstr(env, ARMInstr_NUnary(ARMneon_PADDLU,
4076 HReg res = newVRegV(env);
4077 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4079 addInstr(env, ARMInstr_NUnary(ARMneon_CNT, res, arg, size, True));
4085 HReg res = newVRegV(env);
4086 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4094 addInstr(env, ARMInstr_NUnary(ARMneon_CLZ, res, arg, size, True));
4100 HReg res = newVRegV(env);
4101 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4109 addInstr(env, ARMInstr_NUnary(ARMneon_CLS, res, arg, size, True));
4113 HReg res = newVRegV(env);
4114 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4115 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoS,
4120 HReg res = newVRegV(env);
4121 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4122 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTFtoU,
4127 HReg res = newVRegV(env);
4128 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4129 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTStoF,
4134 HReg res = newVRegV(env);
4135 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4136 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTUtoF,
4141 HReg res = newVRegV(env);
4142 HReg arg = iselNeon64Expr(env, e->Iex.Unop.arg);
4143 addInstr(env, ARMInstr_NUnary(ARMneon_VCVTF16toF32,
4148 HReg res = newVRegV(env);
4149 HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
4150 addInstr(env, ARMInstr_NUnary(ARMneon_VRECIPF,
4155 HReg res = newVRegV(env);
4156 HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
4157 addInstr(env, ARMInstr_NUnary(ARMneon_VRECIP,
4169 HReg res = newVRegV(env);
4170 HReg argL = iselNeonExpr(env, mi.bindee[0]);
4171 HReg argR = iselNeonExpr(env, mi.bindee[1]);
4172 addInstr(env, ARMInstr_NBinary(ARMneon_VABDFP,
4176 HReg res = newVRegV(env);
4177 HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
4178 addInstr(env, ARMInstr_NUnary(ARMneon_VABSFP,
4184 HReg res = newVRegV(env);
4185 HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
4186 addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTEFP,
4191 HReg res = newVRegV(env);
4192 HReg argL = iselNeonExpr(env, e->Iex.Unop.arg);
4193 addInstr(env, ARMInstr_NUnary(ARMneon_VRSQRTE,
4198 HReg res = newVRegV(env);
4199 HReg arg = iselNeonExpr(env, e->Iex.Unop.arg);
4200 addInstr(env, ARMInstr_NUnary(ARMneon_VNEGF,
4216 typeOfIRExpr(env->type_env, e->Iex.Binop.arg1) == Ity_I64 &&
4217 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) == Ity_I64 &&
4223 HReg res = newVRegV(env);
4224 addInstr(env, ARMInstr_NeonImm(res, imm));
4229 HReg tmp1 = newVRegV(env);
4230 HReg tmp2 = newVRegV(env);
4231 HReg res = newVRegV(env);
4233 addInstr(env, ARMInstr_NeonImm(tmp1, ARMNImm_TI(9,0x0f)));
4234 addInstr(env, ARMInstr_NeonImm(tmp2, imm));
4235 addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
4242 HReg tmp1 = newVRegV(env);
4243 HReg tmp2 = newVRegV(env);
4244 HReg res = newVRegV(env);
4246 addInstr(env, ARMInstr_NeonImm(tmp1, ARMNImm_TI(9,0xf0)));
4247 addInstr(env, ARMInstr_NeonImm(tmp2, imm));
4248 addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
4261 HReg res = newVRegV(env);
4268 addInstr(env, ARMInstr_Alu(ARMalu_SUB, hregARM_R13(),
4272 iselInt64Expr(&w1, &w0, env, e->Iex.Binop.arg2);
4273 addInstr(env, ARMInstr_LdSt32(False/*store*/, w0, sp_0));
4274 addInstr(env, ARMInstr_LdSt32(False/*store*/, w1, sp_4));
4277 iselInt64Expr(&w3, &w2, env, e->Iex.Binop.arg1);
4278 addInstr(env, ARMInstr_LdSt32(False/*store*/, w2, sp_8));
4279 addInstr(env, ARMInstr_LdSt32(False/*store*/, w3, sp_12));
4282 addInstr(env, ARMInstr_NLdStQ(True/*load*/, res,
4286 addInstr(env, ARMInstr_Alu(ARMalu_ADD, hregARM_R13(),
4292 HReg res = newVRegV(env);
4293 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4294 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4295 addInstr(env, ARMInstr_NBinary(ARMneon_VAND,
4300 HReg res = newVRegV(env);
4301 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4302 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4303 addInstr(env, ARMInstr_NBinary(ARMneon_VORR,
4308 HReg res = newVRegV(env);
4309 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4310 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4311 addInstr(env, ARMInstr_NBinary(ARMneon_VXOR,
4344 HReg res = newVRegV(env);
4345 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4346 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4357 addInstr(env, ARMInstr_NBinary(ARMneon_VADD,
4362 HReg res = newVRegV(env);
4363 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4364 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4366 addInstr(env, ARMInstr_NBinary(ARMneon_VADDFP,
4371 HReg res = newVRegV(env);
4372 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4373 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4375 addInstr(env, ARMInstr_NBinary(ARMneon_VRECPS,
4380 HReg res = newVRegV(env);
4381 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4382 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4384 addInstr(env, ARMInstr_NBinary(ARMneon_VRSQRTS,
4394 HReg tmp = newVRegV(env);
4395 HReg res = newVRegV(env);
4396 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4397 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4412 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4414 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4416 addInstr(env, ARMInstr_NDual(ARMneon_TRN,
4419 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4421 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4423 addInstr(env, ARMInstr_NDual(ARMneon_TRN,
4434 HReg tmp = newVRegV(env);
4435 HReg res = newVRegV(env);
4436 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4437 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4452 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4454 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4456 addInstr(env, ARMInstr_NDual(ARMneon_ZIP,
4459 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4461 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4463 addInstr(env, ARMInstr_NDual(ARMneon_ZIP,
4474 HReg tmp = newVRegV(env);
4475 HReg res = newVRegV(env);
4476 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4477 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4492 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4494 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4496 addInstr(env, ARMInstr_NDual(ARMneon_UZP,
4499 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4501 addInstr(env, ARMInstr_NUnary(ARMneon_COPY,
4503 addInstr(env, ARMInstr_NDual(ARMneon_UZP,
4512 HReg res = newVRegV(env);
4513 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4514 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4525 addInstr(env, ARMInstr_NBinary(ARMneon_VQADDU,
4533 HReg res = newVRegV(env);
4534 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4535 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4546 addInstr(env, ARMInstr_NBinary(ARMneon_VQADDS,
4554 HReg res = newVRegV(env);
4555 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4556 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4567 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
4572 HReg res = newVRegV(env);
4573 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4574 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4576 addInstr(env, ARMInstr_NBinary(ARMneon_VSUBFP,
4584 HReg res = newVRegV(env);
4585 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4586 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4597 addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBU,
4605 HReg res = newVRegV(env);
4606 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4607 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4618 addInstr(env, ARMInstr_NBinary(ARMneon_VQSUBS,
4625 HReg res = newVRegV(env);
4626 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4627 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4635 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXU,
4642 HReg res = newVRegV(env);
4643 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4644 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4652 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXS,
4659 HReg res = newVRegV(env);
4660 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4661 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4669 addInstr(env, ARMInstr_NBinary(ARMneon_VMINU,
4676 HReg res = newVRegV(env);
4677 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4678 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4686 addInstr(env, ARMInstr_NBinary(ARMneon_VMINS,
4694 HReg res = newVRegV(env);
4695 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4696 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4697 HReg argR2 = newVRegV(env);
4698 HReg zero = newVRegV(env);
4707 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
4708 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
4710 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
4718 HReg res = newVRegV(env);
4719 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4720 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4729 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
4737 HReg res = newVRegV(env);
4738 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4739 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4740 HReg argR2 = newVRegV(env);
4741 HReg zero = newVRegV(env);
4750 addInstr(env, ARMInstr_NeonImm(zero, ARMNImm_TI(0,0)));
4751 addInstr(env, ARMInstr_NBinary(ARMneon_VSUB,
4753 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
4761 HReg res = newVRegV(env);
4762 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4763 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4772 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
4780 HReg res = newVRegV(env);
4781 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4782 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4791 addInstr(env, ARMInstr_NShift(ARMneon_VQSHL,
4799 HReg res = newVRegV(env);
4800 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4801 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4810 addInstr(env, ARMInstr_NShift(ARMneon_VQSAL,
4818 HReg res = newVRegV(env);
4819 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4822 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
4834 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUU,
4842 HReg res = newVRegV(env);
4843 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4846 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
4858 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNUS,
4866 HReg res = newVRegV(env);
4867 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4870 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
4882 addInstr(env, ARMInstr_NUnary(ARMneon_VQSHLNSS,
4890 HReg res = newVRegV(env);
4891 HReg tmp = newVRegV(env);
4892 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4893 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
4894 HReg argR2 = newVRegI(env);
4903 addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
4904 addInstr(env, ARMInstr_NUnary(ARMneon_DUP,
4906 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
4914 HReg res = newVRegV(env);
4915 HReg tmp = newVRegV(env);
4916 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4917 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
4926 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR, 0, True));
4927 addInstr(env, ARMInstr_NShift(ARMneon_VSHL,
4935 HReg res = newVRegV(env);
4936 HReg tmp = newVRegV(env);
4937 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4938 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
4939 HReg argR2 = newVRegI(env);
4948 addInstr(env, ARMInstr_Unary(ARMun_NEG, argR2, argR));
4949 addInstr(env, ARMInstr_NUnary(ARMneon_DUP, tmp, argR2, 0, True));
4950 addInstr(env, ARMInstr_NShift(ARMneon_VSAL,
4957 HReg res = newVRegV(env);
4958 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4959 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4967 env, ARMInstr_NBinary(ARMneon_VCGTU,
4974 HReg res = newVRegV(env);
4975 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4976 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
4984 addInstr(env, ARMInstr_NBinary(ARMneon_VCGTS,
4991 HReg res = newVRegV(env);
4992 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
4993 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5001 addInstr(env, ARMInstr_NBinary(ARMneon_VCEQ,
5008 HReg res = newVRegV(env);
5009 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5010 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5018 addInstr(env, ARMInstr_NBinary(ARMneon_VMUL,
5023 HReg res = newVRegV(env);
5024 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5025 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5027 addInstr(env, ARMInstr_NBinary(ARMneon_VMULFP,
5034 HReg res = newVRegV(env);
5035 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
5036 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
5044 addInstr(env, ARMInstr_NBinary(ARMneon_VMULLU,
5052 HReg res = newVRegV(env);
5053 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
5054 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
5062 addInstr(env, ARMInstr_NBinary(ARMneon_VMULLS,
5069 HReg res = newVRegV(env);
5070 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5071 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5078 addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULH,
5085 HReg res = newVRegV(env);
5086 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5087 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5094 addInstr(env, ARMInstr_NBinary(ARMneon_VQRDMULH,
5101 HReg res = newVRegV(env);
5102 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
5103 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
5110 addInstr(env, ARMInstr_NBinary(ARMneon_VQDMULL,
5115 HReg res = newVRegV(env);
5116 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5117 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5119 addInstr(env, ARMInstr_NBinary(ARMneon_VMULP,
5124 HReg res = newVRegV(env);
5125 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5126 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5127 addInstr(env, ARMInstr_NBinary(ARMneon_VMAXF,
5132 HReg res = newVRegV(env);
5133 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5134 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5135 addInstr(env, ARMInstr_NBinary(ARMneon_VMINF,
5140 HReg res = newVRegV(env);
5141 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5142 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5143 addInstr(env, ARMInstr_NBinary(ARMneon_VPMAXF,
5148 HReg res = newVRegV(env);
5149 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5150 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5151 addInstr(env, ARMInstr_NBinary(ARMneon_VPMINF,
5156 HReg res = newVRegV(env);
5157 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5158 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5159 addInstr(env, ARMInstr_NBinary(ARMneon_VCGTF,
5164 HReg res = newVRegV(env);
5165 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5166 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5167 addInstr(env, ARMInstr_NBinary(ARMneon_VCGEF,
5172 HReg res = newVRegV(env);
5173 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5174 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5175 addInstr(env, ARMInstr_NBinary(ARMneon_VCEQF,
5181 HReg res = newVRegV(env);
5182 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
5183 HReg argR = iselNeon64Expr(env, e->Iex.Binop.arg2);
5185 addInstr(env, ARMInstr_NBinary(ARMneon_VMULLP,
5193 HReg res = newVRegV(env);
5194 HReg arg = iselNeonExpr(env, e->Iex.Binop.arg1);
5198 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
5212 addInstr(env, ARMInstr_NUnary(op, res, arg, imm6, True));
5220 HReg res = newVRegV(env);
5221 HReg argL = iselNeon64Expr(env, e->Iex.Binop.arg1);
5225 typeOfIRExpr(env->type_env, e->Iex.Binop.arg2) != Ity_I8) {
5240 addInstr(env, ARMInstr_NUnary(ARMneon_VDUP,
5248 HReg res = newVRegV(env);
5249 HReg argL = iselNeonExpr(env, e->Iex.Binop.arg1);
5250 HReg argR = iselNeonExpr(env, e->Iex.Binop.arg2);
5258 addInstr(env, ARMInstr_NBinary(ARMneon_VPADD,
5273 HReg res = newVRegV(env);
5274 HReg argL = iselNeonExpr(env, triop->arg1);
5275 HReg argR = iselNeonExpr(env, triop->arg2);
5278 typeOfIRExpr(env->type_env, triop->arg3) != Ity_I8) {
5287 addInstr(env, ARMInstr_NBinary(ARMneon_VEXT,
5298 HReg rX = iselNeonExpr(env, e->Iex.Mux0X.exprX);
5299 HReg r0 = iselNeonExpr(env, e->Iex.Mux0X.expr0);
5300 HReg dst = newVRegV(env);
5301 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, rX, 4, True));
5302 r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
5303 addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8,
5305 addInstr(env, ARMInstr_NCMovQ(ARMcc_EQ, dst, r0));
5323 static HReg iselDblExpr ( ISelEnv* env, IRExpr* e )
5325 HReg r = iselDblExpr_wrk( env, e );
5335 static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
5337 IRType ty = typeOfIRExpr(env->type_env,e);
5342 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
5349 HReg z32 = newVRegI(env);
5350 HReg dst = newVRegD(env);
5351 addInstr(env, ARMInstr_Imm32(z32, 0));
5352 addInstr(env, ARMInstr_VXferD(True/*toD*/, dst, z32, z32));
5359 HReg res = newVRegD(env);
5361 am = iselIntExpr_AModeV(env, e->Iex.Load.addr);
5362 addInstr(env, ARMInstr_VLdStD(True/*isLoad*/, res, am));
5370 HReg res = newVRegD(env);
5371 addInstr(env, ARMInstr_VLdStD(True/*isLoad*/, res, am));
5378 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
5379 return iselNeon64Expr(env, e->Iex.Unop.arg);
5382 HReg dst = newVRegD(env);
5383 iselInt64Expr(&srcHi, &srcLo, env, e->Iex.Unop.arg);
5384 env, ARMInstr_VXferD(True/*toD*/, dst, srcHi, srcLo));
5389 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
5390 HReg dst = newVRegD(env);
5391 addInstr(env, ARMInstr_VUnaryD(ARMvfpu_NEG, dst, src));
5395 HReg src = iselDblExpr(env, e->Iex.Unop.arg);
5396 HReg dst = newVRegD(env);
5397 addInstr(env, ARMInstr_VUnaryD(ARMvfpu_ABS, dst, src));
5401 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
5402 HReg dst = newVRegD(env);
5403 addInstr(env, ARMInstr_VCvtSD(True/*sToD*/, dst, src));
5408 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
5409 HReg f32 = newVRegF(env);
5410 HReg dst = newVRegD(env);
5413 addInstr(env, ARMInstr_VXferS(True/*toS*/, f32, src));
5415 addInstr(env, ARMInstr_VCvtID(True/*iToD*/, syned,
5428 HReg src = iselDblExpr(env, e->Iex.Binop.arg2);
5429 HReg dst = newVRegD(env);
5430 addInstr(env, ARMInstr_VUnaryD(ARMvfpu_SQRT, dst, src));
5447 HReg argL = iselDblExpr(env, triop->arg2);
5448 HReg argR = iselDblExpr(env, triop->arg3);
5449 HReg dst = newVRegD(env);
5457 addInstr(env, ARMInstr_VAluD(op, dst, argL, argR));
5467 && typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8) {
5469 HReg rX = iselDblExpr(env, e->Iex.Mux0X.exprX);
5470 HReg r0 = iselDblExpr(env, e->Iex.Mux0X.expr0);
5471 HReg dst = newVRegD(env);
5472 addInstr(env, ARMInstr_VUnaryD(ARMvfpu_COPY, dst, rX));
5473 r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
5474 addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8,
5476 addInstr(env, ARMInstr_VCMovD(ARMcc_EQ, dst, r0));
5495 static HReg iselFltExpr ( ISelEnv* env, IRExpr* e )
5497 HReg r = iselFltExpr_wrk( env, e );
5507 static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e )
5509 IRType ty = typeOfIRExpr(env->type_env,e);
5514 return lookupIRTemp(env, e->Iex.RdTmp.tmp);
5519 HReg res = newVRegF(env);
5521 am = iselIntExpr_AModeV(env, e->Iex.Load.addr);
5522 addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am));
5530 HReg res = newVRegF(env);
5531 addInstr(env, ARMInstr_VLdStS(True/*isLoad*/, res, am));
5538 HReg dst = newVRegF(env);
5539 HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
5540 addInstr(env, ARMInstr_VXferS(True/*toS*/, dst, src));
5544 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
5545 HReg dst = newVRegF(env);
5546 addInstr(env, ARMInstr_VUnaryS(ARMvfpu_NEG, dst, src));
5550 HReg src = iselFltExpr(env, e->Iex.Unop.arg);
5551 HReg dst = newVRegF(env);
5552 addInstr(env, ARMInstr_VUnaryS(ARMvfpu_ABS, dst, src));
5564 HReg src = iselFltExpr(env, e->Iex.Binop.arg2);
5565 HReg dst = newVRegF(env);
5566 addInstr(env, ARMInstr_VUnaryS(ARMvfpu_SQRT, dst, src));
5570 HReg valD = iselDblExpr(env, e->Iex.Binop.arg2);
5571 set_VFP_rounding_mode(env, e->Iex.Binop.arg1);
5572 HReg valS = newVRegF(env);
5574 addInstr(env, ARMInstr_VCvtSD(False/*!sToD*/, valS, valD));
5575 set_VFP_rounding_default(env);
5592 HReg argL = iselFltExpr(env, triop->arg2);
5593 HReg argR = iselFltExpr(env, triop->arg3);
5594 HReg dst = newVRegF(env);
5602 addInstr(env, ARMInstr_VAluS(op, dst, argL, argR));
5612 && typeOfIRExpr(env->type_env,e->Iex.Mux0X.cond) == Ity_I8) {
5614 HReg rX = iselFltExpr(env, e->Iex.Mux0X.exprX);
5615 HReg r0 = iselFltExpr(env, e->Iex.Mux0X.expr0);
5616 HReg dst = newVRegF(env);
5617 addInstr(env, ARMInstr_VUnaryS(ARMvfpu_COPY, dst, rX));
5618 r8 = iselIntExpr_R(env, e->Iex.Mux0X.cond);
5619 addInstr(env, ARMInstr_CmpOrTst(False/*!isCmp*/, r8,
5621 addInstr(env, ARMInstr_VCMovS(ARMcc_EQ, dst, r0));
5635 static void iselStmt ( ISelEnv* env, IRStmt* stmt )
5647 IRType tya = typeOfIRExpr(env->type_env, stmt->Ist.Store.addr);
5648 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data);
5655 HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
5656 ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Store.addr);
5657 addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rD, am));
5661 HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
5662 ARMAMode2* am = iselIntExpr_AMode2(env, stmt->Ist.Store.addr);
5663 addInstr(env, ARMInstr_LdSt16(False/*!isLoad*/,
5668 HReg rD = iselIntExpr_R(env, stmt->Ist.Store.data);
5669 ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Store.addr);
5670 addInstr(env, ARMInstr_LdSt8U(False/*!isLoad*/, rD, am));
5674 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
5675 HReg dD = iselNeon64Expr(env, stmt->Ist.Store.data);
5676 ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr);
5677 addInstr(env, ARMInstr_NLdStD(False, dD, am));
5680 iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Store.data);
5681 rA = iselIntExpr_R(env, stmt->Ist.Store.addr);
5682 addInstr(env, ARMInstr_LdSt32(False/*!load*/, rDhi,
5684 addInstr(env, ARMInstr_LdSt32(False/*!load*/, rDlo,
5690 HReg dD = iselDblExpr(env, stmt->Ist.Store.data);
5691 ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr);
5692 addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, dD, am));
5696 HReg fD = iselFltExpr(env, stmt->Ist.Store.data);
5697 ARMAModeV* am = iselIntExpr_AModeV(env, stmt->Ist.Store.addr);
5698 addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, fD, am));
5702 HReg qD = iselNeonExpr(env, stmt->Ist.Store.data);
5703 ARMAModeN* am = iselIntExpr_AModeN(env, stmt->Ist.Store.addr);
5704 addInstr(env, ARMInstr_NLdStQ(False, qD, am));
5714 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Put.data);
5717 HReg rD = iselIntExpr_R(env, stmt->Ist.Put.data);
5719 addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rD, am));
5723 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
5724 HReg addr = newVRegI(env);
5725 HReg qD = iselNeon64Expr(env, stmt->Ist.Put.data);
5726 addInstr(env, ARMInstr_Add32(addr, hregARM_R8(),
5728 addInstr(env, ARMInstr_NLdStD(False, qD, mkARMAModeN_R(addr)));
5735 iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.Put.data);
5736 addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rDhi, am4));
5737 addInstr(env, ARMInstr_LdSt32(False/*!isLoad*/, rDlo, am0));
5745 HReg rD = iselDblExpr(env, stmt->Ist.Put.data);
5746 addInstr(env, ARMInstr_VLdStD(False/*!isLoad*/, rD, am));
5753 HReg rD = iselFltExpr(env, stmt->Ist.Put.data);
5754 addInstr(env, ARMInstr_VLdStS(False/*!isLoad*/, rD, am));
5758 HReg addr = newVRegI(env);
5759 HReg qD = iselNeonExpr(env, stmt->Ist.Put.data);
5760 addInstr(env, ARMInstr_Add32(addr, hregARM_R8(),
5762 addInstr(env, ARMInstr_NLdStQ(False, qD, mkARMAModeN_R(addr)));
5773 //zz env, stmt->Ist.PutI.descr,
5776 //zz IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.PutI.data);
5779 //zz HReg reg = iselIntExpr_R(env, stmt->Ist.PutI.data);
5780 //zz addInstr(env, ARMInstr_StoreB(reg, am2));
5791 IRType ty = typeOfIRTemp(env->type_env, tmp);
5795 env, stmt->Ist.WrTmp.data);
5796 HReg dst = lookupIRTemp(env, tmp);
5797 addInstr(env, ARMInstr_Mov(dst,ri84));
5801 HReg dst = lookupIRTemp(env, tmp);
5802 ARMCondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data);
5803 addInstr(env, ARMInstr_Mov(dst, ARMRI84_I84(0,0)));
5804 addInstr(env, ARMInstr_CMov(cond, dst, ARMRI84_I84(1,0)));
5808 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
5809 HReg src = iselNeon64Expr(env, stmt->Ist.WrTmp.data);
5810 HReg dst = lookupIRTemp(env, tmp);
5811 addInstr(env, ARMInstr_NUnary(ARMneon_COPY, dst, src, 4, False));
5814 iselInt64Expr(&rHi,&rLo, env, stmt->Ist.WrTmp.data);
5815 lookupIRTemp64( &dstHi, &dstLo, env, tmp);
5816 addInstr(env, mk_iMOVds_RR(dstHi, rHi) );
5817 addInstr(env, mk_iMOVds_RR(dstLo, rLo) );
5822 HReg src = iselDblExpr(env, stmt->Ist.WrTmp.data);
5823 HReg dst = lookupIRTemp(env, tmp);
5824 addInstr(env, ARMInstr_VUnaryD(ARMvfpu_COPY, dst, src));
5828 HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data);
5829 HReg dst = lookupIRTemp(env, tmp);
5830 addInstr(env, ARMInstr_VUnaryS(ARMvfpu_COPY, dst, src));
5834 HReg src = iselNeonExpr(env, stmt->Ist.WrTmp.data);
5835 HReg dst = lookupIRTemp(env, tmp);
5836 addInstr(env
5855 Bool ok = doHelperCall( env, passBBP, d->guard, d->cee, d->args );
5864 retty = typeOfIRTemp(env->type_env, d->tmp);
5867 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
5868 HReg tmp = lookupIRTemp(env, d->tmp);
5869 addInstr(env, ARMInstr_VXferD(True, tmp, hregARM_R1(),
5875 lookupIRTemp64( &dstHi, &dstLo, env, d->tmp);
5876 addInstr(env, mk_iMOVds_RR(dstHi, hregARM_R1()) );
5877 addInstr(env, mk_iMOVds_RR(dstLo, hregARM_R0()) );
5884 HReg dst = lookupIRTemp(env, d->tmp);
5885 addInstr(env, mk_iMOVds_RR(dst, hregARM_R0()) );
5897 IRType ty = typeOfIRTemp(env->type_env, res);
5900 HReg r_dst = lookupIRTemp(env, res);
5901 HReg raddr = iselIntExpr_R(env, stmt->Ist.LLSC.addr);
5908 addInstr(env, mk_iMOVds_RR(hregARM_R4(), raddr));
5909 addInstr(env, ARMInstr_LdrEX(szB));
5910 addInstr(env, mk_iMOVds_RR(r_dst, hregARM_R2()));
5914 HReg raddr = iselIntExpr_R(env, stmt->Ist.LLSC.addr);
5915 addInstr(env, mk_iMOVds_RR(hregARM_R4(), raddr));
5916 addInstr(env, ARMInstr_LdrEX(8));
5921 if (env->hwcaps & VEX_HWCAPS_ARM_NEON) {
5922 HReg dst = lookupIRTemp(env, res);
5923 addInstr(env, ARMInstr_VXferD(True, dst, hregARM_R3(),
5927 lookupIRTemp64(&r_dst_hi, &r_dst_lo, env, res);
5928 addInstr(env, mk_iMOVds_RR(r_dst_lo, hregARM_R2()));
5929 addInstr(env, mk_iMOVds_RR(r_dst_hi, hregARM_R3()));
5937 IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.storedata);
5940 HReg rD = iselIntExpr_R(env, stmt->Ist.LLSC.storedata);
5941 HReg rA = iselIntExpr_R(env, stmt->Ist.LLSC.addr);
5948 addInstr(env, mk_iMOVds_RR(hregARM_R2(), rD));
5949 addInstr(env, mk_iMOVds_RR(hregARM_R4(), rA));
5950 addInstr(env, ARMInstr_StrEX(szB));
5959 iselInt64Expr(&rDhi, &rDlo, env, stmt->Ist.LLSC.storedata);
5960 HReg rA = iselIntExpr_R(env, stmt->Ist.LLSC.addr);
5961 addInstr(env, mk_iMOVds_RR(hregARM_R2(), rDlo));
5962 addInstr(env, mk_iMOVds_RR(hregARM_R3(), rDhi));
5963 addInstr(env, mk_iMOVds_RR(hregARM_R4(), rA));
5964 addInstr(env, ARMInstr_StrEX(8));
5970 IRType ty = typeOfIRTemp(env->type_env, res);
5971 HReg r_res = lookupIRTemp(env, res);
5974 addInstr(env, ARMInstr_Alu(ARMalu_XOR, r_res, hregARM_R0(), one));
5976 addInstr(env, ARMInstr_Alu(ARMalu_AND, r_res, r_res, one));
5986 addInstr(env, ARMInstr_MFence());
5989 addInstr(env, ARMInstr_CLREX());
6010 ARMCondCode cc = iselCondCode(env, stmt->Ist.Exit.guard);
6018 if (env->chainingAllowed) {
6023 = ((Addr32)stmt->Ist.Exit.dst->Ico.U32) > env->max_ga;
6025 addInstr(env, ARMInstr_XDirect(stmt->Ist.Exit.dst->Ico.U32,
6031 HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
6032 addInstr(env, ARMInstr_XAssisted(r, amR15T, cc, Ijk_Boring));
6046 HReg r = iselIntExpr_R(env, IRExpr_Const(stmt->Ist.Exit.dst));
6047 addInstr(env, ARMInstr_XAssisted(r, amR15T, cc,
6071 static void iselNext ( ISelEnv* env,
6089 if (env->chainingAllowed) {
6094 = ((Addr64)cdst->Ico.U32) > env->max_ga;
6096 addInstr(env, ARMInstr_XDirect(cdst->Ico.U32,
6103 HReg r = iselIntExpr_R(env, next);
6104 addInstr(env, ARMInstr_XAssisted(r, amR15T, ARMcc_AL,
6114 HReg r = iselIntExpr_R(env, next);
6116 if (env->chainingAllowed) {
6117 addInstr(env, ARMInstr_XIndir(r, amR15T, ARMcc_AL));
6119 addInstr(env, ARMInstr_XAssisted(r, amR15T, ARMcc_AL,
6136 HReg r = iselIntExpr_R(env, next);
6138 addInstr(env, ARMInstr_XAssisted(r, amR15T, ARMcc_AL, jk));
6172 ISelEnv* env;
6183 env = LibVEX_Alloc(sizeof(ISelEnv));
6184 env->vreg_ctr = 0;
6187 env->code = newHInstrArray();
6189 /* Copy BB's type env. */
6190 env->type_env = bb->tyenv;
6194 env->n_vregmap = bb->tyenv->types_used;
6195 env->vregmap = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
6196 env->vregmapHI = LibVEX_Alloc(env->n_vregmap * sizeof(HReg));
6199 env->chainingAllowed = chainingAllowed;
6200 env->hwcaps = hwcaps_host;
6201 env->max_ga = max_ga;
6206 for (i = 0; i < env->n_vregmap; i++) {
6227 env->vregmap[i] = hreg;
6228 env->vregmapHI[i] = hregHI;
6230 env->vreg_ctr = j;
6235 addInstr(env, ARMInstr_EvCheck(amCounter, amFailAddr));
6242 addInstr(env, ARMInstr_ProfInc());
6247 iselStmt(env, bb->stmts[i]);
6249 iselNext(env, bb->next, bb->jumpkind, bb->offsIP);
6252 env->code->n_vregs = env->vreg_ctr;
6253 return env->code;
