Lines Matching refs:mode64
41 void ppHRegMIPS(HReg reg, Bool mode64)
104 HReg hregMIPS_GPR0(Bool mode64)
106 return MkHRegGPR(0, mode64);
109 HReg hregMIPS_GPR1(Bool mode64)
111 return MkHRegGPR(1, mode64);
114 HReg hregMIPS_GPR2(Bool mode64)
116 return MkHRegGPR(2, mode64);
119 HReg hregMIPS_GPR3(Bool mode64)
121 return MkHRegGPR(3, mode64);
124 HReg hregMIPS_GPR4(Bool mode64)
126 return MkHRegGPR(4, mode64);
129 HReg hregMIPS_GPR5(Bool mode64)
131 return MkHRegGPR(5, mode64);
134 HReg hregMIPS_GPR6(Bool mode64)
136 return MkHRegGPR(6, mode64);
139 HReg hregMIPS_GPR7(Bool mode64)
141 return MkHRegGPR(7, mode64);
144 HReg hregMIPS_GPR8(Bool mode64)
146 return MkHRegGPR(8, mode64);
149 HReg hregMIPS_GPR9(Bool mode64)
151 return MkHRegGPR(9, mode64);
154 HReg hregMIPS_GPR10(Bool mode64)
156 return MkHRegGPR(10, mode64);
159 HReg hregMIPS_GPR11(Bool mode64)
161 return MkHRegGPR(11, mode64);
164 HReg hregMIPS_GPR12(Bool mode64)
166 return MkHRegGPR(12, mode64);
169 HReg hregMIPS_GPR13(Bool mode64)
171 return MkHRegGPR(13, mode64);
174 HReg hregMIPS_GPR14(Bool mode64)
176 return MkHRegGPR(14, mode64);
179 HReg hregMIPS_GPR15(Bool mode64)
181 return MkHRegGPR(15, mode64);
184 HReg hregMIPS_GPR16(Bool mode64)
186 return MkHRegGPR(16, mode64);
189 HReg hregMIPS_GPR17(Bool mode64)
191 return MkHRegGPR(17, mode64);
194 HReg hregMIPS_GPR18(Bool mode64)
196 return MkHRegGPR(18, mode64);
199 HReg hregMIPS_GPR19(Bool mode64)
201 return MkHRegGPR(19, mode64);
204 HReg hregMIPS_GPR20(Bool mode64)
206 return MkHRegGPR(20, mode64);
209 HReg hregMIPS_GPR21(Bool mode64)
211 return MkHRegGPR(21, mode64);
214 HReg hregMIPS_GPR22(Bool mode64)
216 return MkHRegGPR(22, mode64);
219 HReg hregMIPS_GPR23(Bool mode64)
221 return MkHRegGPR(23, mode64);
224 HReg hregMIPS_GPR24(Bool mode64)
226 return MkHRegGPR(24, mode64);
229 HReg hregMIPS_GPR25(Bool mode64)
231 return MkHRegGPR(25, mode64);
234 HReg hregMIPS_GPR26(Bool mode64)
236 return MkHRegGPR(26, mode64);
239 HReg hregMIPS_GPR27(Bool mode64)
241 return MkHRegGPR(27, mode64);
244 HReg hregMIPS_GPR28(Bool mode64)
246 return MkHRegGPR(28, mode64);
249 HReg hregMIPS_GPR29(Bool mode64)
251 return MkHRegGPR(29, mode64);
254 HReg hregMIPS_GPR30(Bool mode64)
256 return MkHRegGPR(30, mode64);
259 HReg hregMIPS_GPR31(Bool mode64)
261 return MkHRegGPR(31, mode64);
267 HReg hregMIPS_F0(Bool mode64)
269 return MkHRegFPR(0, mode64);
272 HReg hregMIPS_F1(Bool mode64)
274 return MkHRegFPR(1, mode64);
277 HReg hregMIPS_F2(Bool mode64)
279 return MkHRegFPR(2, mode64);
282 HReg hregMIPS_F3(Bool mode64)
284 return MkHRegFPR(3, mode64);
287 HReg hregMIPS_F4(Bool mode64)
289 return MkHRegFPR(4, mode64);
292 HReg hregMIPS_F5(Bool mode64)
294 return MkHRegFPR(5, mode64);
297 HReg hregMIPS_F6(Bool mode64)
299 return MkHRegFPR(6, mode64);
302 HReg hregMIPS_F7(Bool mode64)
304 return MkHRegFPR(7, mode64);
307 HReg hregMIPS_F8(Bool mode64)
309 return MkHRegFPR(8, mode64);
312 HReg hregMIPS_F9(Bool mode64)
314 return MkHRegFPR(9, mode64);
317 HReg hregMIPS_F10(Bool mode64)
319 return MkHRegFPR(10, mode64);
322 HReg hregMIPS_F11(Bool mode64)
324 return MkHRegFPR(11, mode64);
327 HReg hregMIPS_F12(Bool mode64)
329 return MkHRegFPR(12, mode64);
332 HReg hregMIPS_F13(Bool mode64)
334 return MkHRegFPR(13, mode64);
337 HReg hregMIPS_F14(Bool mode64)
339 return MkHRegFPR(14, mode64);
342 HReg hregMIPS_F15(Bool mode64)
344 return MkHRegFPR(15, mode64);
347 HReg hregMIPS_F16(Bool mode64)
349 return MkHRegFPR(16, mode64);
352 HReg hregMIPS_F17(Bool mode64)
354 return MkHRegFPR(17, mode64);
357 HReg hregMIPS_F18(Bool mode64)
359 return MkHRegFPR(18, mode64);
362 HReg hregMIPS_F19(Bool mode64)
364 return MkHRegFPR(19, mode64);
367 HReg hregMIPS_F20(Bool mode64)
369 return MkHRegFPR(20, mode64);
372 HReg hregMIPS_F21(Bool mode64)
374 return MkHRegFPR(21, mode64);
377 HReg hregMIPS_F22(Bool mode64)
379 return MkHRegFPR(22, mode64);
382 HReg hregMIPS_F23(Bool mode64)
384 return MkHRegFPR(23, mode64);
387 HReg hregMIPS_F24(Bool mode64)
389 return MkHRegFPR(24, mode64);
392 HReg hregMIPS_F25(Bool mode64)
394 return MkHRegFPR(25, mode64);
397 HReg hregMIPS_F26(Bool mode64)
399 return MkHRegFPR(26, mode64);
402 HReg hregMIPS_F27(Bool mode64)
404 return MkHRegFPR(27, mode64);
407 HReg hregMIPS_F28(Bool mode64)
409 return MkHRegFPR(28, mode64);
412 HReg hregMIPS_F29(Bool mode64)
414 return MkHRegFPR(29, mode64);
417 HReg hregMIPS_F30(Bool mode64)
419 return MkHRegFPR(30, mode64);
422 HReg hregMIPS_F31(Bool mode64)
424 return MkHRegFPR(31, mode64);
427 HReg hregMIPS_PC(Bool mode64)
429 return mkHReg(32, mode64 ? HRcFlt64 : HRcFlt32, False);
432 HReg hregMIPS_HI(Bool mode64)
434 return mkHReg(33, mode64 ? HRcFlt64 : HRcFlt32, False);
437 HReg hregMIPS_LO(Bool mode64)
439 return mkHReg(34, mode64 ? HRcFlt64 : HRcFlt32, False);
552 void getAllocableRegs_MIPS(Int * nregs, HReg ** arr, Bool mode64)
554 if (mode64)
565 (*arr)[i++] = hregMIPS_GPR16(mode64);
566 (*arr)[i++] = hregMIPS_GPR17(mode64);
567 (*arr)[i++] = hregMIPS_GPR18(mode64);
568 (*arr)[i++] = hregMIPS_GPR19(mode64);
569 (*arr)[i++] = hregMIPS_GPR20(mode64);
570 (*arr)[i++] = hregMIPS_GPR21(mode64);
571 (*arr)[i++] = hregMIPS_GPR22(mode64);
572 if (!mode64)
573 (*arr)[i++] = hregMIPS_GPR23(mode64);
576 if (mode64) {
577 (*arr)[i++] = hregMIPS_GPR8(mode64);
578 (*arr)[i++] = hregMIPS_GPR9(mode64);
579 (*arr)[i++] = hregMIPS_GPR10(mode64);
580 (*arr)[i++] = hregMIPS_GPR11(mode64);
582 (*arr)[i++] = hregMIPS_GPR12(mode64);
583 (*arr)[i++] = hregMIPS_GPR13(mode64);
584 (*arr)[i++] = hregMIPS_GPR14(mode64);
585 (*arr)[i++] = hregMIPS_GPR15(mode64);
586 (*arr)[i++] = hregMIPS_GPR24(mode64);
598 (*arr)[i++] = hregMIPS_F20(mode64);
599 (*arr)[i++] = hregMIPS_F21(mode64);
600 (*arr)[i++] = hregMIPS_F22(mode64);
601 (*arr)[i++] = hregMIPS_F23(mode64);
602 (*arr)[i++] = hregMIPS_F24(mode64);
603 (*arr)[i++] = hregMIPS_F25(mode64);
604 (*arr)[i++] = hregMIPS_F26(mode64);
605 (*arr)[i++] = hregMIPS_F27(mode64);
606 (*arr)[i++] = hregMIPS_F28(mode64);
607 (*arr)[i++] = hregMIPS_F29(mode64);
608 (*arr)[i++] = hregMIPS_F30(mode64);
609 if (!mode64) {
892 void ppMIPSAMode(MIPSAMode * am, Bool mode64)
900 ppHRegMIPS(am->Mam.IR.base, mode64);
904 ppHRegMIPS(am->Mam.RR.base, mode64);
906 ppHRegMIPS(am->Mam.RR.index, mode64);
970 void ppMIPSRH(MIPSRH * op, Bool mode64)
981 ppHRegMIPS(op->Mrh.Reg.reg, mode64);
1281 MIPSInstr *MIPSInstr_Load(UChar sz, HReg dst, MIPSAMode * src, Bool mode64)
1291 vassert(mode64);
1295 MIPSInstr *MIPSInstr_Store(UChar sz, MIPSAMode * dst, HReg src, Bool mode64)
1305 vassert(mode64);
1309 MIPSInstr *MIPSInstr_LoadL(UChar sz, HReg dst, MIPSAMode * src, Bool mode64)
1319 vassert(mode64);
1323 MIPSInstr *MIPSInstr_StoreC(UChar sz, MIPSAMode * dst, HReg src, Bool mode64)
1333 vassert(mode64);
1481 static void ppLoadImm(HReg dst, ULong imm, Bool mode64)
1484 ppHRegMIPS(dst, mode64);
1488 void ppMIPSInstr(MIPSInstr * i, Bool mode64)
1492 ppLoadImm(i->Min.LI.dst, i->Min.LI.imm, mode64
1500 ppHRegMIPS(i->Min.Alu.dst, mode64);
1502 ppHRegMIPS(r_srcL, mode64);
1504 ppMIPSRH(rh_srcR, mode64);
1513 ppHRegMIPS(i->Min.Shft.dst, mode64);
1515 ppHRegMIPS(r_srcL, mode64);
1517 ppMIPSRH(rh_srcR, mode64);
1522 ppHRegMIPS(i->Min.Unary.dst, mode64);
1524 ppHRegMIPS(i->Min.Unary.src, mode64);
1529 ppHRegMIPS(i->Min.Cmp.dst, mode64);
1531 ppHRegMIPS(i->Min.Cmp.srcL, mode64);
1533 ppHRegMIPS(i->Min.Cmp.srcR, mode64);
1542 ppHRegMIPS(i->Min.Mul.dst, mode64);
1544 ppHRegMIPS(i->Min.Mul.srcL, mode64);
1546 ppHRegMIPS(i->Min.Mul.srcR, mode64);
1551 ppHRegMIPS(i->Min.Mul.dst, mode64);
1553 ppHRegMIPS(i->Min.Mul.srcL, mode64);
1555 ppHRegMIPS(i->Min.Mul.srcR, mode64);
1562 ppHRegMIPS(i->Min.MtHL.src, mode64);
1567 ppHRegMIPS(i->Min.MtHL.src, mode64);
1572 ppHRegMIPS(i->Min.MfHL.dst, mode64);
1577 ppHRegMIPS(i->Min.MfHL.dst, mode64);
1582 ppHRegMIPS(i->Min.Macc.srcL, mode64);
1584 ppHRegMIPS(i->Min.Macc.srcR, mode64);
1592 ppHRegMIPS(i->Min.Div.srcL, mode64);
1594 ppHRegMIPS(i->Min.Div.srcR, mode64);
1604 ppLoadImm(hregMIPS_GPR11(mode64), i->Min.Call.target, mode64);
1623 ppMIPSAMode(i->Min.XDirect.amPC, mode64);
1631 ppHRegMIPS(i->Min.XIndir.dstGA, mode64);
1633 ppMIPSAMode(i->Min.XIndir.amPC, mode64);
1641 ppHRegMIPS(i->Min.XAssisted.dstGA, mode64);
1643 ppMIPSAMode(i->Min.XAssisted.amPC, mode64);
1653 ppHRegMIPS(i->Min.Load.dst, mode64);
1655 ppMIPSAMode(i->Min.Load.src, mode64);
1663 ppHRegMIPS(i->Min.Store.src, mode64);
1665 ppMIPSAMode(i->Min.Store.dst, mode64);
1670 ppHRegMIPS(i->Min.LoadL.dst, mode64);
1672 ppMIPSAMode(i->Min.LoadL.src, mode64);
1677 ppHRegMIPS(i->Min.StoreC.src, mode64);
1679 ppMIPSAMode(i->Min.StoreC.dst, mode64);
1684 ppHRegMIPS(i->Min.RdWrLR.gpr, mode64);
1689 ppHRegMIPS(i->Min.FpUnary.dst, mode64);
1691 ppHRegMIPS(i->Min.FpUnary.src, mode64);
1695 ppHRegMIPS(i->Min.FpBinary.dst, mode64);
1697 ppHRegMIPS(i->Min.FpBinary.srcL, mode64);
1699 ppHRegMIPS(i->Min.FpBinary.srcR, mode64);
1703 ppHRegMIPS(i->Min.FpConvert.dst, mode64);
1705 ppHRegMIPS(i->Min.FpConvert.src, mode64);
1709 ppHRegMIPS(i->Min.FpCompare.srcL, mode64);
1711 ppHRegMIPS(i->Min.FpCompare.srcR, mode64);
1716 ppHRegMIPS(i->Min.FpMulAcc.dst, mode64);
1718 ppHRegMIPS(i->Min.FpMulAcc.srcML, mode64);
1720 ppHRegMIPS(i->Min.FpMulAcc.srcMR, mode64);
1722 ppHRegMIPS(i->Min.FpMulAcc.srcAcc, mode64);
1728 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1730 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1733 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1735 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1739 if (mode64)
1743 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1745 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1747 if (mode64)
1751 ppHRegMIPS(i->Min.FpLdSt.reg, mode64);
1753 ppMIPSAMode(i->Min.FpLdSt.addr, mode64);
1768 ppHRegMIPS(i->Min.MtFCSR.src, mode64);
1775 ppHRegMIPS(i->Min.MfFCSR.dst, mode64);
1781 ppMIPSAMode(i->Min.EvCheck.amCounter, mode64);
1784 ppMIPSAMode(i->Min.EvCheck.amCounter, mode64);
1786 ppMIPSAMode(i->Min.EvCheck.amFailAddr, mode64);
1807 void getRegUsage_MIPSInstr(HRegUsage * u, MIPSInstr * i, Bool mode64)
1840 addHRegUse(u, HRmWrite, hregMIPS_HI(mode64));
1841 addHRegUse(u, HRmWrite, hregMIPS_LO(mode64));
1846 addHRegUse(u, HRmRead, hregMIPS_HI(mode64));
1847 addHRegUse(u, HRmRead, hregMIPS_LO(mode64));
1857 addHRegUse(u, HRmModify, hregMIPS_HI(mode64));
1858 addHRegUse(u, HRmModify, hregMIPS_LO(mode64));
1863 addHRegUse(u, HRmWrite, hregMIPS_HI(mode64));
1864 addHRegUse(u, HRmWrite, hregMIPS_LO(mode64));
1872 addHRegUse(u, HRmWrite, hregMIPS_GPR1(mode64));
1874 addHRegUse(u, HRmWrite, hregMIPS_GPR2(mode64));
1875 addHRegUse(u, HRmWrite, hregMIPS_GPR3(mode64));
1877 addHRegUse(u, HRmWrite, hregMIPS_GPR4(mode64));
1878 addHRegUse(u, HRmWrite, hregMIPS_GPR5(mode64));
1879 addHRegUse(u, HRmWrite, hregMIPS_GPR6(mode64));
1880 addHRegUse(u, HRmWrite, hregMIPS_GPR7(mode64));
1882 addHRegUse(u, HRmWrite, hregMIPS_GPR8(mode64));
1883 addHRegUse(u, HRmWrite, hregMIPS_GPR9(mode64));
1884 addHRegUse(u, HRmWrite, hregMIPS_GPR10(mode64));
1885 addHRegUse(u, HRmWrite, hregMIPS_GPR11(mode64));
1886 addHRegUse(u, HRmWrite, hregMIPS_GPR12(mode64));
1887 addHRegUse(u, HRmWrite, hregMIPS_GPR13(mode64));
1888 addHRegUse(u, HRmWrite, hregMIPS_GPR14(mode64));
1889 addHRegUse(u, HRmWrite, hregMIPS_GPR15(mode64));
1891 addHRegUse(u, HRmWrite, hregMIPS_GPR24(mode64));
1892 addHRegUse(u, HRmWrite, hregMIPS_GPR25(mode64));
1893 addHRegUse(u, HRmWrite, hregMIPS_GPR26(mode64));
1894 addHRegUse(u, HRmWrite, hregMIPS_GPR27(mode64));
1900 addHRegUse(u, HRmRead, hregMIPS_GPR7(mode64));
1902 addHRegUse(u, HRmRead, hregMIPS_GPR6(mode64));
1904 addHRegUse(u, HRmRead, hregMIPS_GPR5(mode64));
1906 addHRegUse(u, HRmRead, hregMIPS_GPR4(mode64));
1955 if (mode64) {
2010 ppMIPSInstr(i, mode64);
2022 void mapRegs_MIPSInstr(HRegRemap * m, MIPSInstr * i, Bool mode64)
2110 if (mode64) {
2170 ppMIPSInstr(i, mode64);
2203 Int offsetB, Bool mode64)
2209 am = MIPSAMode_IR(offsetB, GuestStatePointer(mode64));
2213 vassert(mode64);
2214 *i1 = MIPSInstr_Store(8, am, rreg, mode64);
2217 vassert(!mode64);
2218 *i1 = MIPSInstr_Store(4, am, rreg, mode64);
2221 vassert(!mode64);
2235 Int offsetB, Bool mode64)
2239 am = MIPSAMode_IR(offsetB, GuestStatePointer(mode64));
2243 vassert(mode64);
2244 *i1 = MIPSInstr_Load(8, rreg, am, mode64);
2247 vassert(!mode64);
2248 *i1 = MIPSInstr_Load(4, rreg, am, mode64);
2251 if (mode64)
2268 static UInt iregNo(HReg r, Bool mode64)
2271 vassert(hregClass(r) == mode64 ? HRcInt64 : HRcInt32);
2278 static UChar fregNo(HReg r, Bool mode64)
2281 vassert(hregClass(r) == mode64 ? HRcFlt64 : HRcFlt32);
2392 Bool mode64)
2398 rA = iregNo(am->Mam.IR.base, mode64);
2432 Bool mode64)
2437 rA = iregNo(am->Mam.RR.base, mode64);
2438 rB = iregNo(am->Mam.RR.index, mode64);
2460 if (mode64) {
2489 static UChar *mkLoadImm(UChar * p, UInt r_dst, ULong imm, Bool mode64)
2491 if (!mode64) {
2512 vassert(mode64);
2535 UInt r_dst, ULong imm, Bool mode64 )
2539 if (!mode64) {
2548 if (!mode64) {
2564 UInt r_dst, ULong imm, Bool mode64 )
2568 if (!mode64) {
2577 if (!mode64) {
2599 UInt reg, MIPSAMode* am, Bool mode64 )
2602 UInt opc1, sz = mode64 ? 8 : 4;
2605 if (mode64) {
2620 vassert(mode64);
2626 p = doAMode_IR(p, opc1, reg, am, mode64);
2638 UInt opc1, sz = mode64 ? 8 : 4;
2641 if (mode64) {
2655 vassert(mode64);
2662 p = doAMode_IR(p, opc1, reg, am, mode64);
2697 Bool mode64,
2710 UInt condR = iregNo(i->Min.MovCond.condR, mode64);
2711 UInt dst = iregNo(i->Min.MovCond.dst, mode64);
2713 UInt srcL = iregNo(i->Min.MovCond.srcL, mode64);
2724 p = mkMoveReg(p, dst, iregNo(srcR->Mrh.Reg.reg, mode64));
2725 /*p = mkFormR(p, 0, dst, iregNo(src->Mrh.Reg.reg, mode64),
2726 iregNo(src->Mrh.Reg.reg, mode64), 0, 37);*/
2728 p = mkLoadImm(p, dst, srcR->Mrh.Imm.imm16, mode64);
2734 p = mkLoadImm(p, iregNo(i->Min.LI.dst, mode64), i->Min.LI.imm, mode64);
2740 UInt r_dst = iregNo(i->Min.Alu.dst, mode64);
2741 UInt r_srcL = iregNo(i->Min.Alu.srcL, mode64);
2742 UInt r_srcR = immR ? (-1) /*bogus */ : iregNo(srcR->Mrh.Reg.reg, mode64);
2830 UInt r_dst = iregNo(i->Min.Shft.dst, mode64);
2831 UInt r_srcL = iregNo(i->Min.Shft.srcL, mode64);
2833 mode64);
2834 if (!mode64)
2924 UInt r_dst = iregNo(i->Min.Unary.dst, mode64);
2925 UInt r_src = iregNo(i->Min.Unary.src, mode64);
2943 UInt r_srcL = iregNo(i->Min.Cmp.srcL, mode64);
2944 UInt r_srcR = iregNo(i->Min.Cmp.srcR, mode64);
2945 UInt r_dst = iregNo(i->Min.Cmp.dst, mode64);
3008 UInt r_srcL = iregNo(i->Min.Mul.srcL, mode64);
3009 UInt r_srcR = iregNo(i->Min.Mul.srcR, mode64);
3010 UInt r_dst = iregNo(i->Min.Mul.dst, mode64);
3030 else if (mode64 && !sz32)
3040 UInt r_srcL = iregNo(i->Min.Macc.srcL, mode64);
3041 UInt r_srcR = iregNo(i->Min.Macc.srcR, mode64);
3080 UInt r_srcL = iregNo(i->Min.Div.srcL, mode64);
3081 UInt r_srcR = iregNo(i->Min.Div.srcR, mode64);
3102 UInt r_src = iregNo(i->Min.MtHL.src, mode64);
3108 UInt r_src = iregNo(i->Min.MtHL.src, mode64);
3114 UInt r_dst = iregNo(i->Min.MfHL.dst, mode64);
3120 UInt r_dst = iregNo(i->Min.MfHL.dst, mode64);
3126 UInt r_src = iregNo(i->Min.MtFCSR.src, mode64);
3133 UInt r_dst = iregNo(i->Min.MfFCSR.dst, mode64);
3154 p = mkLoadImm(p, r_dst, i->Min.Call.target, mode64);
3162 UInt r_src = iregNo(i->Min.Call.src, mode64);
3200 (ULong)i->Min.XDirect.dstGA, mode64);
3202 /*r*/9, i->Min.XDirect.amPC, mode64);
3215 Ptr_to_ULong(disp_cp_chain_me), mode64);
3260 iregNo(i->Min.XIndir.dstGA, mode64),
3261 i->Min.XIndir.amPC, mode64);
3267 Ptr_to_ULong(disp_cp_xindir), mode64);
3300 iregNo(i->Min.XIndir.dstGA, mode64),
3301 i->Min.XIndir.amPC, mode64);
3329 p = mkLoadImm_EXACTLY2or5(p, /*r*/10, trcval, mode64);
3333 (ULong)Ptr_to_ULong(disp_cp_xassisted), mode64);
3357 UInt r_dst = iregNo(i->Min.Load.dst, mode64);
3359 if (mode64 && (sz == 4 || sz == 8)) {
3375 vassert(mode64);
3381 p = doAMode_IR(p, opc, r_dst, am_addr, mode64);
3384 UInt r_dst = iregNo(i->Min.Load.dst, mode64);
3399 vassert(mode64);
3405 p = doAMode_RR(p, opc, r_dst, am_addr, mode64);
3414 UInt r_src = iregNo(i->Min.Store.src, mode64);
3416 if (mode64 && (sz == 4 || sz == 8)) {
3431 vassert(mode64);
3438 p = doAMode_IR(p, opc, r_src, am_addr, mode64);
3441 UInt r_src = iregNo(i->Min.Store.src, mode64);
3455 vassert(mode64);
3462 mode64);
3469 UInt r_src = iregNo(am_addr->Mam.IR.base, mode64);
3471 UInt r_dst = iregNo(i->Min.LoadL.dst, mode64);
3478 UInt r_src = iregNo(i->Min.StoreC.src, mode64);
3480 UInt r_dst = iregNo(am_addr->Mam.IR.base, mode64);
3486 UInt reg = iregNo(i->Min.RdWrLR.gpr, mode64);
3502 UInt f_reg = fregNo(i->Min.FpLdSt.reg, mode64);
3505 p = doAMode_IR(p, 0x31, f_reg, am_addr, mode64);
3507 p = doAMode_RR(p, 0x31, f_reg, am_addr, mode64);
3510 p = doAMode_IR(p, 0x39, f_reg, am_addr, mode64);
3512 p = doAMode_RR(p, 0x39, f_reg, am_addr, mode64);
3518 if (mode64) {
3519 p = doAMode_IR(p, 0x35, f_reg, am_addr, mode64);
3521 p = doAMode_IR(p, 0x31, f_reg, am_addr, mode64);
3523 nextMIPSAModeFloat(am_addr), mode64);
3526 if (mode64) {
3527 p = doAMode_RR(p, 0x35, f_reg, am_addr, mode64);
3529 p = doAMode_RR(p, 0x31, f_reg, am_addr, mode64);
3531 nextMIPSAModeFloat(am_addr), mode64);
3536 if (mode64) {
3537 p = doAMode_IR(p, 0x3d, f_reg, am_addr, mode64);
3539 p = doAMode_IR(p, 0x39, f_reg, am_addr, mode64);
3541 nextMIPSAModeFloat(am_addr), mode64);
3544 if (mode64) {
3545 p = doAMode_RR(p, 0x3d, f_reg, am_addr, mode64);
3547 p = doAMode_RR(p, 0x39, f_reg, am_addr, mode64);
3549 nextMIPSAModeFloat(am_addr), mode64);
3560 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3561 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3572 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3573 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3584 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3585 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3597 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3602 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3603 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3614 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3615 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3626 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64);
3627 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64);
3646 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3647 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3648 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3653 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3654 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3655 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3660 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3661 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3662 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3667 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64);
3668 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64);
3669 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64);
3711 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3716 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3717 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3721 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3726 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3727 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3732 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3736 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3737 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3741 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3746 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3756 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3757 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3761 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3767 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3776 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3777 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3781 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3786 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3787 fr_src = fregNo(i->Min.FpConvert.src, mode64);
3791 fr_dst = fregNo(i->Min.FpConvert.dst, mode64);
3803 UInt r_dst = iregNo(i->Min.FpCompare.dst, mode64);
3833 i->Min.EvCheck.amCounter, mode64);
3838 i->Min.EvCheck.amCounter, mode64);
3843 i->Min.EvCheck.amFailAddr, mode64);
3870 if (mode64) {
3875 False/*!mode64*/);
3911 ppMIPSInstr(i, mode64);
3932 Bool mode64 )
3947 mode64));
3948 vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x120F809);
3949 vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x00000000);
3963 Ptr_to_ULong(place_to_jump_to), mode64);
3968 vassert(len == (mode64 ? 28 : 16)); /* stay sane */
3978 Bool mode64 )
3993 mode64));
3994 vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x120F809);
3995 vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x00000000);
4007 Ptr_to_ULong(disp_cp_chain_me), mode64);
4012 vassert(len == (mode64 ? 28 : 16)); /* stay sane */
4020 ULong* location_of_counter, Bool mode64 )
4025 vassert(isLoadImm_EXACTLY2or5((UChar *)p, /*r*/9, 0x65556555, mode64));
4027 vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x8D280000);
4028 vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x25080001);
4029 vassert(fetch32(p + (mode64 ? 20 : 8) + 8) == 0xAD280000);
4030 vassert(fetch32(p + (mode64 ? 20 : 8) + 12) == 0x2d010001);
4031 vassert(fetch32(p + (mode64 ? 20 : 8) + 16) == 0x8d280004);
4032 vassert(fetch32(p + (mode64 ? 20 : 8) + 20) == 0x01014021);
4033 vassert(fetch32(p + (mode64 ? 20 : 8) + 24) == 0xad280004);
4036 Ptr_to_ULong(location_of_counter), mode64);
