Lines Matching defs:srcStep
26 srcStep RN 1
73 VLD1 dSrc0, [pSrc], srcStep ;// [a0 a1 a2 a3 .. ]
74 ADD Temp, pSrc, srcStep, LSL #2
75 VLD1 dSrc1, [pSrc], srcStep ;// [b0 b1 b2 b3 .. ]
77 VLD1 dSrc5, [Temp], srcStep
79 VLD1 dSrc2, [pSrc], srcStep ;// [c0 c1 c2 c3 .. ]
81 VLD1 dSrc3, [pSrc], srcStep
83 VLD1 dSrc6, [Temp], srcStep ;// TeRi
85 VLD1 dSrc4, [pSrc], srcStep
86 VLD1 dSrc7, [Temp], srcStep ;// TeRi
89 VLD1 dSrc8, [Temp], srcStep ;// TeRi
94 ; VLD1 dSrc6, [Temp], srcStep
102 ; VLD1 dSrc7, [Temp], srcStep
110 ; VLD1 dSrc8, [Temp], srcStep ;// [i0 i1 i2 i3 .. ]
