HomeSort by relevance Sort by last modified time
    Searched defs:DefIdx (Results 1 - 8 of 8) sorted by null

  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.h 136 unsigned DefIdx;
154 return DefIdx-1;
  /external/llvm/lib/CodeGen/
LiveRangeCalc.cpp 91 unsigned DefIdx;
95 } else if (MI->isRegTiedToDefOperand(I.getOperandNo(), &DefIdx)) {
98 if (MI->getOperand(DefIdx).isEarlyClobber())
TargetSchedule.cpp 150 unsigned DefIdx = 0;
154 ++DefIdx;
156 return DefIdx;
214 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
215 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
218 STI->getWriteLatencyEntry(SCDesc, DefIdx);
231 // If DefIdx does not exist in the model (e.g. implicit defs), then return
238 ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
259 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries
    [all...]
RegAllocFast.cpp 735 unsigned DefIdx = 0;
736 if (!MI->isRegTiedToDefOperand(i, &DefIdx)) continue;
738 << DefIdx << ".\n");
    [all...]
InlineSpiller.cpp 888 SlotIndex DefIdx = Edit->rematerializeAt(*MI->getParent(), MI, NewLI.reg, RM,
890 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t
    [all...]
MachineInstr.cpp 700 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
701 if (DefIdx != -1)
702 tieOperands(DefIdx, OpNo);
    [all...]
MachineVerifier.cpp 874 unsigned DefIdx;
876 MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
877 Reg != MI->getOperand(DefIdx).getReg())
    [all...]
RegisterCoalescer.cpp 599 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
600 assert(DefIdx != -1);
602 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
702 SlotIndex DefIdx = UseIdx.getRegSlot();
703 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
706 DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI);
707 assert(DVNI->def == DefIdx);
    [all...]

Completed in 198 milliseconds