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      1 /*
      2  * i386 virtual CPU header
      3  *
      4  *  Copyright (c) 2003 Fabrice Bellard
      5  *
      6  * This library is free software; you can redistribute it and/or
      7  * modify it under the terms of the GNU Lesser General Public
      8  * License as published by the Free Software Foundation; either
      9  * version 2 of the License, or (at your option) any later version.
     10  *
     11  * This library is distributed in the hope that it will be useful,
     12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14  * Lesser General Public License for more details.
     15  *
     16  * You should have received a copy of the GNU Lesser General Public
     17  * License along with this library; if not, write to the Free Software
     18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
     19  */
     20 #ifndef CPU_I386_H
     21 #define CPU_I386_H
     22 
     23 #include "config.h"
     24 
     25 #ifdef TARGET_X86_64
     26 #define TARGET_LONG_BITS 64
     27 #else
     28 #define TARGET_LONG_BITS 32
     29 #endif
     30 
     31 /* target supports implicit self modifying code */
     32 #define TARGET_HAS_SMC
     33 /* support for self modifying code even if the modified instruction is
     34    close to the modifying instruction */
     35 #define TARGET_HAS_PRECISE_SMC
     36 
     37 #define TARGET_HAS_ICE 1
     38 
     39 #ifdef TARGET_X86_64
     40 #define ELF_MACHINE	EM_X86_64
     41 #else
     42 #define ELF_MACHINE	EM_386
     43 #endif
     44 
     45 #define CPUState struct CPUX86State
     46 
     47 #include "cpu-defs.h"
     48 
     49 #include "softfloat.h"
     50 
     51 #define R_EAX 0
     52 #define R_ECX 1
     53 #define R_EDX 2
     54 #define R_EBX 3
     55 #define R_ESP 4
     56 #define R_EBP 5
     57 #define R_ESI 6
     58 #define R_EDI 7
     59 
     60 #define R_AL 0
     61 #define R_CL 1
     62 #define R_DL 2
     63 #define R_BL 3
     64 #define R_AH 4
     65 #define R_CH 5
     66 #define R_DH 6
     67 #define R_BH 7
     68 
     69 #define R_ES 0
     70 #define R_CS 1
     71 #define R_SS 2
     72 #define R_DS 3
     73 #define R_FS 4
     74 #define R_GS 5
     75 
     76 /* segment descriptor fields */
     77 #define DESC_G_MASK     (1 << 23)
     78 #define DESC_B_SHIFT    22
     79 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
     80 #define DESC_L_SHIFT    21 /* x86_64 only : 64 bit code segment */
     81 #define DESC_L_MASK     (1 << DESC_L_SHIFT)
     82 #define DESC_AVL_MASK   (1 << 20)
     83 #define DESC_P_MASK     (1 << 15)
     84 #define DESC_DPL_SHIFT  13
     85 #define DESC_DPL_MASK   (3 << DESC_DPL_SHIFT)
     86 #define DESC_S_MASK     (1 << 12)
     87 #define DESC_TYPE_SHIFT 8
     88 #define DESC_TYPE_MASK  (15 << DESC_TYPE_SHIFT)
     89 #define DESC_A_MASK     (1 << 8)
     90 
     91 #define DESC_CS_MASK    (1 << 11) /* 1=code segment 0=data segment */
     92 #define DESC_C_MASK     (1 << 10) /* code: conforming */
     93 #define DESC_R_MASK     (1 << 9)  /* code: readable */
     94 
     95 #define DESC_E_MASK     (1 << 10) /* data: expansion direction */
     96 #define DESC_W_MASK     (1 << 9)  /* data: writable */
     97 
     98 #define DESC_TSS_BUSY_MASK (1 << 9)
     99 
    100 /* eflags masks */
    101 #define CC_C   	0x0001
    102 #define CC_P 	0x0004
    103 #define CC_A	0x0010
    104 #define CC_Z	0x0040
    105 #define CC_S    0x0080
    106 #define CC_O    0x0800
    107 
    108 #define TF_SHIFT   8
    109 #define IOPL_SHIFT 12
    110 #define VM_SHIFT   17
    111 
    112 #define TF_MASK 		0x00000100
    113 #define IF_MASK 		0x00000200
    114 #define DF_MASK 		0x00000400
    115 #define IOPL_MASK		0x00003000
    116 #define NT_MASK	         	0x00004000
    117 #define RF_MASK			0x00010000
    118 #define VM_MASK			0x00020000
    119 #define AC_MASK			0x00040000
    120 #define VIF_MASK                0x00080000
    121 #define VIP_MASK                0x00100000
    122 #define ID_MASK                 0x00200000
    123 
    124 /* hidden flags - used internally by qemu to represent additional cpu
    125    states. Only the CPL, INHIBIT_IRQ, SMM and SVMI are not
    126    redundant. We avoid using the IOPL_MASK, TF_MASK and VM_MASK bit
    127    position to ease oring with eflags. */
    128 /* current cpl */
    129 #define HF_CPL_SHIFT         0
    130 /* true if soft mmu is being used */
    131 #define HF_SOFTMMU_SHIFT     2
    132 /* true if hardware interrupts must be disabled for next instruction */
    133 #define HF_INHIBIT_IRQ_SHIFT 3
    134 /* 16 or 32 segments */
    135 #define HF_CS32_SHIFT        4
    136 #define HF_SS32_SHIFT        5
    137 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
    138 #define HF_ADDSEG_SHIFT      6
    139 /* copy of CR0.PE (protected mode) */
    140 #define HF_PE_SHIFT          7
    141 #define HF_TF_SHIFT          8 /* must be same as eflags */
    142 #define HF_MP_SHIFT          9 /* the order must be MP, EM, TS */
    143 #define HF_EM_SHIFT         10
    144 #define HF_TS_SHIFT         11
    145 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
    146 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
    147 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
    148 #define HF_RF_SHIFT         16 /* must be same as eflags */
    149 #define HF_VM_SHIFT         17 /* must be same as eflags */
    150 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
    151 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
    152 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
    153 #define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
    154 
    155 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
    156 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
    157 #define HF_INHIBIT_IRQ_MASK  (1 << HF_INHIBIT_IRQ_SHIFT)
    158 #define HF_CS32_MASK         (1 << HF_CS32_SHIFT)
    159 #define HF_SS32_MASK         (1 << HF_SS32_SHIFT)
    160 #define HF_ADDSEG_MASK       (1 << HF_ADDSEG_SHIFT)
    161 #define HF_PE_MASK           (1 << HF_PE_SHIFT)
    162 #define HF_TF_MASK           (1 << HF_TF_SHIFT)
    163 #define HF_MP_MASK           (1 << HF_MP_SHIFT)
    164 #define HF_EM_MASK           (1 << HF_EM_SHIFT)
    165 #define HF_TS_MASK           (1 << HF_TS_SHIFT)
    166 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
    167 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
    168 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
    169 #define HF_RF_MASK           (1 << HF_RF_SHIFT)
    170 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
    171 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
    172 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
    173 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
    174 #define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
    175 
    176 /* hflags2 */
    177 
    178 #define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
    179 #define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
    180 #define HF2_NMI_SHIFT        2 /* CPU serving NMI */
    181 #define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
    182 
    183 #define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
    184 #define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT)
    185 #define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
    186 #define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
    187 
    188 #define CR0_PE_SHIFT 0
    189 #define CR0_MP_SHIFT 1
    190 
    191 #define CR0_PE_MASK  (1 << 0)
    192 #define CR0_MP_MASK  (1 << 1)
    193 #define CR0_EM_MASK  (1 << 2)
    194 #define CR0_TS_MASK  (1 << 3)
    195 #define CR0_ET_MASK  (1 << 4)
    196 #define CR0_NE_MASK  (1 << 5)
    197 #define CR0_WP_MASK  (1 << 16)
    198 #define CR0_AM_MASK  (1 << 18)
    199 #define CR0_PG_MASK  (1 << 31)
    200 
    201 #define CR4_VME_MASK  (1 << 0)
    202 #define CR4_PVI_MASK  (1 << 1)
    203 #define CR4_TSD_MASK  (1 << 2)
    204 #define CR4_DE_MASK   (1 << 3)
    205 #define CR4_PSE_MASK  (1 << 4)
    206 #define CR4_PAE_MASK  (1 << 5)
    207 #define CR4_MCE_MASK  (1 << 6)
    208 #define CR4_PGE_MASK  (1 << 7)
    209 #define CR4_PCE_MASK  (1 << 8)
    210 #define CR4_OSFXSR_SHIFT 9
    211 #define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT)
    212 #define CR4_OSXMMEXCPT_MASK  (1 << 10)
    213 
    214 #define DR6_BD          (1 << 13)
    215 #define DR6_BS          (1 << 14)
    216 #define DR6_BT          (1 << 15)
    217 #define DR6_FIXED_1     0xffff0ff0
    218 
    219 #define DR7_GD          (1 << 13)
    220 #define DR7_TYPE_SHIFT  16
    221 #define DR7_LEN_SHIFT   18
    222 #define DR7_FIXED_1     0x00000400
    223 
    224 #define PG_PRESENT_BIT	0
    225 #define PG_RW_BIT	1
    226 #define PG_USER_BIT	2
    227 #define PG_PWT_BIT	3
    228 #define PG_PCD_BIT	4
    229 #define PG_ACCESSED_BIT	5
    230 #define PG_DIRTY_BIT	6
    231 #define PG_PSE_BIT	7
    232 #define PG_GLOBAL_BIT	8
    233 #define PG_NX_BIT	63
    234 
    235 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
    236 #define PG_RW_MASK	 (1 << PG_RW_BIT)
    237 #define PG_USER_MASK	 (1 << PG_USER_BIT)
    238 #define PG_PWT_MASK	 (1 << PG_PWT_BIT)
    239 #define PG_PCD_MASK	 (1 << PG_PCD_BIT)
    240 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
    241 #define PG_DIRTY_MASK	 (1 << PG_DIRTY_BIT)
    242 #define PG_PSE_MASK	 (1 << PG_PSE_BIT)
    243 #define PG_GLOBAL_MASK	 (1 << PG_GLOBAL_BIT)
    244 #define PG_NX_MASK	 (1LL << PG_NX_BIT)
    245 
    246 #define PG_ERROR_W_BIT     1
    247 
    248 #define PG_ERROR_P_MASK    0x01
    249 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
    250 #define PG_ERROR_U_MASK    0x04
    251 #define PG_ERROR_RSVD_MASK 0x08
    252 #define PG_ERROR_I_D_MASK  0x10
    253 
    254 #define MCG_CTL_P      (1UL<<8)   /* MCG_CAP register available */
    255 
    256 #define MCE_CAP_DEF    MCG_CTL_P
    257 #define MCE_BANKS_DEF  10
    258 
    259 #define MCG_STATUS_MCIP        (1UL<<2)   /* machine check in progress */
    260 
    261 #define MCI_STATUS_VAL (1ULL<<63)  /* valid error */
    262 #define MCI_STATUS_OVER        (1ULL<<62)  /* previous errors lost */
    263 #define MCI_STATUS_UC  (1ULL<<61)  /* uncorrected error */
    264 
    265 #define MSR_IA32_TSC                    0x10
    266 #define MSR_IA32_APICBASE               0x1b
    267 #define MSR_IA32_APICBASE_BSP           (1<<8)
    268 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
    269 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
    270 
    271 #define MSR_MTRRcap			0xfe
    272 #define MSR_MTRRcap_VCNT		8
    273 #define MSR_MTRRcap_FIXRANGE_SUPPORT	(1 << 8)
    274 #define MSR_MTRRcap_WC_SUPPORTED	(1 << 10)
    275 
    276 #define MSR_IA32_SYSENTER_CS            0x174
    277 #define MSR_IA32_SYSENTER_ESP           0x175
    278 #define MSR_IA32_SYSENTER_EIP           0x176
    279 
    280 #define MSR_MCG_CAP                     0x179
    281 #define MSR_MCG_STATUS                  0x17a
    282 #define MSR_MCG_CTL                     0x17b
    283 
    284 #define MSR_IA32_PERF_STATUS            0x198
    285 
    286 #define MSR_MTRRphysBase(reg)		(0x200 + 2 * (reg))
    287 #define MSR_MTRRphysMask(reg)		(0x200 + 2 * (reg) + 1)
    288 
    289 #define MSR_MTRRfix64K_00000		0x250
    290 #define MSR_MTRRfix16K_80000		0x258
    291 #define MSR_MTRRfix16K_A0000		0x259
    292 #define MSR_MTRRfix4K_C0000		0x268
    293 #define MSR_MTRRfix4K_C8000		0x269
    294 #define MSR_MTRRfix4K_D0000		0x26a
    295 #define MSR_MTRRfix4K_D8000		0x26b
    296 #define MSR_MTRRfix4K_E0000		0x26c
    297 #define MSR_MTRRfix4K_E8000		0x26d
    298 #define MSR_MTRRfix4K_F0000		0x26e
    299 #define MSR_MTRRfix4K_F8000		0x26f
    300 
    301 #define MSR_PAT                         0x277
    302 
    303 #define MSR_MTRRdefType			0x2ff
    304 
    305 #define MSR_MC0_CTL                    0x400
    306 #define MSR_MC0_STATUS                 0x401
    307 #define MSR_MC0_ADDR                   0x402
    308 #define MSR_MC0_MISC                   0x403
    309 
    310 #define MSR_EFER                        0xc0000080
    311 
    312 #define MSR_EFER_SCE   (1 << 0)
    313 #define MSR_EFER_LME   (1 << 8)
    314 #define MSR_EFER_LMA   (1 << 10)
    315 #define MSR_EFER_NXE   (1 << 11)
    316 #define MSR_EFER_SVME  (1 << 12)
    317 #define MSR_EFER_FFXSR (1 << 14)
    318 
    319 #define MSR_STAR                        0xc0000081
    320 #define MSR_LSTAR                       0xc0000082
    321 #define MSR_CSTAR                       0xc0000083
    322 #define MSR_FMASK                       0xc0000084
    323 #define MSR_FSBASE                      0xc0000100
    324 #define MSR_GSBASE                      0xc0000101
    325 #define MSR_KERNELGSBASE                0xc0000102
    326 
    327 #define MSR_VM_HSAVE_PA                 0xc0010117
    328 
    329 /* cpuid_features bits */
    330 #define CPUID_FP87 (1 << 0)
    331 #define CPUID_VME  (1 << 1)
    332 #define CPUID_DE   (1 << 2)
    333 #define CPUID_PSE  (1 << 3)
    334 #define CPUID_TSC  (1 << 4)
    335 #define CPUID_MSR  (1 << 5)
    336 #define CPUID_PAE  (1 << 6)
    337 #define CPUID_MCE  (1 << 7)
    338 #define CPUID_CX8  (1 << 8)
    339 #define CPUID_APIC (1 << 9)
    340 #define CPUID_SEP  (1 << 11) /* sysenter/sysexit */
    341 #define CPUID_MTRR (1 << 12)
    342 #define CPUID_PGE  (1 << 13)
    343 #define CPUID_MCA  (1 << 14)
    344 #define CPUID_CMOV (1 << 15)
    345 #define CPUID_PAT  (1 << 16)
    346 #define CPUID_PSE36   (1 << 17)
    347 #define CPUID_PN   (1 << 18)
    348 #define CPUID_CLFLUSH (1 << 19)
    349 #define CPUID_DTS (1 << 21)
    350 #define CPUID_ACPI (1 << 22)
    351 #define CPUID_MMX  (1 << 23)
    352 #define CPUID_FXSR (1 << 24)
    353 #define CPUID_SSE  (1 << 25)
    354 #define CPUID_SSE2 (1 << 26)
    355 #define CPUID_SS (1 << 27)
    356 #define CPUID_HT (1 << 28)
    357 #define CPUID_TM (1 << 29)
    358 #define CPUID_IA64 (1 << 30)
    359 #define CPUID_PBE (1 << 31)
    360 
    361 #define CPUID_EXT_SSE3     (1 << 0)
    362 #define CPUID_EXT_DTES64   (1 << 2)
    363 #define CPUID_EXT_MONITOR  (1 << 3)
    364 #define CPUID_EXT_DSCPL    (1 << 4)
    365 #define CPUID_EXT_VMX      (1 << 5)
    366 #define CPUID_EXT_SMX      (1 << 6)
    367 #define CPUID_EXT_EST      (1 << 7)
    368 #define CPUID_EXT_TM2      (1 << 8)
    369 #define CPUID_EXT_SSSE3    (1 << 9)
    370 #define CPUID_EXT_CID      (1 << 10)
    371 #define CPUID_EXT_CX16     (1 << 13)
    372 #define CPUID_EXT_XTPR     (1 << 14)
    373 #define CPUID_EXT_PDCM     (1 << 15)
    374 #define CPUID_EXT_DCA      (1 << 18)
    375 #define CPUID_EXT_SSE41    (1 << 19)
    376 #define CPUID_EXT_SSE42    (1 << 20)
    377 #define CPUID_EXT_X2APIC   (1 << 21)
    378 #define CPUID_EXT_MOVBE    (1 << 22)
    379 #define CPUID_EXT_POPCNT   (1 << 23)
    380 #define CPUID_EXT_XSAVE    (1 << 26)
    381 #define CPUID_EXT_OSXSAVE  (1 << 27)
    382 
    383 #define CPUID_EXT2_SYSCALL (1 << 11)
    384 #define CPUID_EXT2_MP      (1 << 19)
    385 #define CPUID_EXT2_NX      (1 << 20)
    386 #define CPUID_EXT2_MMXEXT  (1 << 22)
    387 #define CPUID_EXT2_FFXSR   (1 << 25)
    388 #define CPUID_EXT2_PDPE1GB (1 << 26)
    389 #define CPUID_EXT2_RDTSCP  (1 << 27)
    390 #define CPUID_EXT2_LM      (1 << 29)
    391 #define CPUID_EXT2_3DNOWEXT (1 << 30)
    392 #define CPUID_EXT2_3DNOW   (1 << 31)
    393 
    394 #define CPUID_EXT3_LAHF_LM (1 << 0)
    395 #define CPUID_EXT3_CMP_LEG (1 << 1)
    396 #define CPUID_EXT3_SVM     (1 << 2)
    397 #define CPUID_EXT3_EXTAPIC (1 << 3)
    398 #define CPUID_EXT3_CR8LEG  (1 << 4)
    399 #define CPUID_EXT3_ABM     (1 << 5)
    400 #define CPUID_EXT3_SSE4A   (1 << 6)
    401 #define CPUID_EXT3_MISALIGNSSE (1 << 7)
    402 #define CPUID_EXT3_3DNOWPREFETCH (1 << 8)
    403 #define CPUID_EXT3_OSVW    (1 << 9)
    404 #define CPUID_EXT3_IBS     (1 << 10)
    405 #define CPUID_EXT3_SKINIT  (1 << 12)
    406 
    407 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
    408 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
    409 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
    410 
    411 #define CPUID_VENDOR_AMD_1   0x68747541 /* "Auth" */
    412 #define CPUID_VENDOR_AMD_2   0x69746e65 /* "enti" */
    413 #define CPUID_VENDOR_AMD_3   0x444d4163 /* "cAMD" */
    414 
    415 #define CPUID_MWAIT_IBE     (1 << 1) /* Interrupts can exit capability */
    416 #define CPUID_MWAIT_EMX     (1 << 0) /* enumeration supported */
    417 
    418 #define EXCP00_DIVZ	0
    419 #define EXCP01_DB	1
    420 #define EXCP02_NMI	2
    421 #define EXCP03_INT3	3
    422 #define EXCP04_INTO	4
    423 #define EXCP05_BOUND	5
    424 #define EXCP06_ILLOP	6
    425 #define EXCP07_PREX	7
    426 #define EXCP08_DBLE	8
    427 #define EXCP09_XERR	9
    428 #define EXCP0A_TSS	10
    429 #define EXCP0B_NOSEG	11
    430 #define EXCP0C_STACK	12
    431 #define EXCP0D_GPF	13
    432 #define EXCP0E_PAGE	14
    433 #define EXCP10_COPR	16
    434 #define EXCP11_ALGN	17
    435 #define EXCP12_MCHK	18
    436 
    437 #define EXCP_SYSCALL    0x100 /* only happens in user only emulation
    438                                  for syscall instruction */
    439 
    440 enum {
    441     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
    442     CC_OP_EFLAGS,  /* all cc are explicitly computed, CC_SRC = flags */
    443 
    444     CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
    445     CC_OP_MULW,
    446     CC_OP_MULL,
    447     CC_OP_MULQ,
    448 
    449     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    450     CC_OP_ADDW,
    451     CC_OP_ADDL,
    452     CC_OP_ADDQ,
    453 
    454     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    455     CC_OP_ADCW,
    456     CC_OP_ADCL,
    457     CC_OP_ADCQ,
    458 
    459     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    460     CC_OP_SUBW,
    461     CC_OP_SUBL,
    462     CC_OP_SUBQ,
    463 
    464     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
    465     CC_OP_SBBW,
    466     CC_OP_SBBL,
    467     CC_OP_SBBQ,
    468 
    469     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
    470     CC_OP_LOGICW,
    471     CC_OP_LOGICL,
    472     CC_OP_LOGICQ,
    473 
    474     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
    475     CC_OP_INCW,
    476     CC_OP_INCL,
    477     CC_OP_INCQ,
    478 
    479     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
    480     CC_OP_DECW,
    481     CC_OP_DECL,
    482     CC_OP_DECQ,
    483 
    484     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
    485     CC_OP_SHLW,
    486     CC_OP_SHLL,
    487     CC_OP_SHLQ,
    488 
    489     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
    490     CC_OP_SARW,
    491     CC_OP_SARL,
    492     CC_OP_SARQ,
    493 
    494     CC_OP_NB,
    495 };
    496 
    497 #ifdef FLOATX80
    498 #define USE_X86LDOUBLE
    499 #endif
    500 
    501 #ifdef USE_X86LDOUBLE
    502 typedef floatx80 CPU86_LDouble;
    503 #else
    504 typedef float64 CPU86_LDouble;
    505 #endif
    506 
    507 typedef struct SegmentCache {
    508     uint32_t selector;
    509     target_ulong base;
    510     uint32_t limit;
    511     uint32_t flags;
    512 } SegmentCache;
    513 
    514 typedef union {
    515     uint8_t _b[16];
    516     uint16_t _w[8];
    517     uint32_t _l[4];
    518     uint64_t _q[2];
    519     float32 _s[4];
    520     float64 _d[2];
    521 } XMMReg;
    522 
    523 typedef union {
    524     uint8_t _b[8];
    525     uint16_t _w[4];
    526     uint32_t _l[2];
    527     float32 _s[2];
    528     uint64_t q;
    529 } MMXReg;
    530 
    531 #ifdef WORDS_BIGENDIAN
    532 #define XMM_B(n) _b[15 - (n)]
    533 #define XMM_W(n) _w[7 - (n)]
    534 #define XMM_L(n) _l[3 - (n)]
    535 #define XMM_S(n) _s[3 - (n)]
    536 #define XMM_Q(n) _q[1 - (n)]
    537 #define XMM_D(n) _d[1 - (n)]
    538 
    539 #define MMX_B(n) _b[7 - (n)]
    540 #define MMX_W(n) _w[3 - (n)]
    541 #define MMX_L(n) _l[1 - (n)]
    542 #define MMX_S(n) _s[1 - (n)]
    543 #else
    544 #define XMM_B(n) _b[n]
    545 #define XMM_W(n) _w[n]
    546 #define XMM_L(n) _l[n]
    547 #define XMM_S(n) _s[n]
    548 #define XMM_Q(n) _q[n]
    549 #define XMM_D(n) _d[n]
    550 
    551 #define MMX_B(n) _b[n]
    552 #define MMX_W(n) _w[n]
    553 #define MMX_L(n) _l[n]
    554 #define MMX_S(n) _s[n]
    555 #endif
    556 #define MMX_Q(n) q
    557 
    558 #ifdef TARGET_X86_64
    559 #define CPU_NB_REGS 16
    560 #else
    561 #define CPU_NB_REGS 8
    562 #endif
    563 
    564 #define NB_MMU_MODES 2
    565 
    566 typedef struct CPUX86State {
    567     /* standard registers */
    568     target_ulong regs[CPU_NB_REGS];
    569     target_ulong eip;
    570     target_ulong eflags; /* eflags register. During CPU emulation, CC
    571                         flags and DF are set to zero because they are
    572                         stored elsewhere */
    573 
    574     /* emulator internal eflags handling */
    575     target_ulong cc_src;
    576     target_ulong cc_dst;
    577     uint32_t cc_op;
    578     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
    579     uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
    580                         are known at translation time. */
    581     uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
    582 
    583     /* segments */
    584     SegmentCache segs[6]; /* selector values */
    585     SegmentCache ldt;
    586     SegmentCache tr;
    587     SegmentCache gdt; /* only base and limit are used */
    588     SegmentCache idt; /* only base and limit are used */
    589 
    590     target_ulong cr[5]; /* NOTE: cr1 is unused */
    591     uint64_t a20_mask;
    592 
    593     /* FPU state */
    594     unsigned int fpstt; /* top of stack index */
    595     unsigned int fpus;
    596     unsigned int fpuc;
    597     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
    598     union {
    599 #ifdef USE_X86LDOUBLE
    600         CPU86_LDouble d __attribute__((aligned(16)));
    601 #else
    602         CPU86_LDouble d;
    603 #endif
    604         MMXReg mmx;
    605     } fpregs[8];
    606 
    607     /* emulator internal variables */
    608     float_status fp_status;
    609     CPU86_LDouble ft0;
    610 
    611     float_status mmx_status; /* for 3DNow! float ops */
    612     float_status sse_status;
    613     uint32_t mxcsr;
    614     XMMReg xmm_regs[CPU_NB_REGS];
    615     XMMReg xmm_t0;
    616     MMXReg mmx_t0;
    617     target_ulong cc_tmp; /* temporary for rcr/rcl */
    618 
    619     /* sysenter registers */
    620     uint32_t sysenter_cs;
    621     target_ulong sysenter_esp;
    622     target_ulong sysenter_eip;
    623     uint64_t efer;
    624     uint64_t star;
    625 
    626     uint64_t vm_hsave;
    627     uint64_t vm_vmcb;
    628     uint64_t tsc_offset;
    629     uint64_t intercept;
    630     uint16_t intercept_cr_read;
    631     uint16_t intercept_cr_write;
    632     uint16_t intercept_dr_read;
    633     uint16_t intercept_dr_write;
    634     uint32_t intercept_exceptions;
    635     uint8_t v_tpr;
    636 
    637 #ifdef TARGET_X86_64
    638     target_ulong lstar;
    639     target_ulong cstar;
    640     target_ulong fmask;
    641     target_ulong kernelgsbase;
    642 #endif
    643 
    644     uint64_t tsc;
    645 
    646     uint64_t pat;
    647 
    648     /* exception/interrupt handling */
    649     int error_code;
    650     int exception_is_int;
    651     target_ulong exception_next_eip;
    652     target_ulong dr[8]; /* debug registers */
    653     union {
    654         CPUBreakpoint *cpu_breakpoint[4];
    655         CPUWatchpoint *cpu_watchpoint[4];
    656     }; /* break/watchpoints for dr[0..3] */
    657     uint32_t smbase;
    658     int old_exception;  /* exception in flight */
    659 
    660     CPU_COMMON
    661 
    662     /* processor features (e.g. for CPUID insn) */
    663     uint32_t cpuid_level;
    664     uint32_t cpuid_vendor1;
    665     uint32_t cpuid_vendor2;
    666     uint32_t cpuid_vendor3;
    667     uint32_t cpuid_version;
    668     uint32_t cpuid_features;
    669     uint32_t cpuid_ext_features;
    670     uint32_t cpuid_xlevel;
    671     uint32_t cpuid_model[12];
    672     uint32_t cpuid_ext2_features;
    673     uint32_t cpuid_ext3_features;
    674     uint32_t cpuid_apic_id;
    675     int cpuid_vendor_override;
    676 
    677     /* MTRRs */
    678     uint64_t mtrr_fixed[11];
    679     uint64_t mtrr_deftype;
    680     struct {
    681         uint64_t base;
    682         uint64_t mask;
    683     } mtrr_var[8];
    684 
    685 #ifdef CONFIG_KQEMU
    686     int kqemu_enabled;
    687     int last_io_time;
    688 #endif
    689 
    690     /* For KVM */
    691     uint64_t interrupt_bitmap[256 / 64];
    692     uint32_t mp_state;
    693 
    694     /* in order to simplify APIC support, we leave this pointer to the
    695        user */
    696     struct APICState *apic_state;
    697 
    698     uint64 mcg_cap;
    699     uint64 mcg_status;
    700     uint64 mcg_ctl;
    701     uint64 *mce_banks;
    702 } CPUX86State;
    703 
    704 CPUX86State *cpu_x86_init(const char *cpu_model);
    705 int cpu_x86_exec(CPUX86State *s);
    706 void cpu_x86_close(CPUX86State *s);
    707 void x86_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt,
    708                                                  ...));
    709 int cpu_get_pic_interrupt(CPUX86State *s);
    710 /* MSDOS compatibility mode FPU exception support */
    711 void cpu_set_ferr(CPUX86State *s);
    712 
    713 /* this function must always be used to load data in the segment
    714    cache: it synchronizes the hflags with the segment cache values */
    715 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
    716                                           int seg_reg, unsigned int selector,
    717                                           target_ulong base,
    718                                           unsigned int limit,
    719                                           unsigned int flags)
    720 {
    721     SegmentCache *sc;
    722     unsigned int new_hflags;
    723 
    724     sc = &env->segs[seg_reg];
    725     sc->selector = selector;
    726     sc->base = base;
    727     sc->limit = limit;
    728     sc->flags = flags;
    729 
    730     /* update the hidden flags */
    731     {
    732         if (seg_reg == R_CS) {
    733 #ifdef TARGET_X86_64
    734             if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
    735                 /* long mode */
    736                 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
    737                 env->hflags &= ~(HF_ADDSEG_MASK);
    738             } else
    739 #endif
    740             {
    741                 /* legacy / compatibility case */
    742                 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
    743                     >> (DESC_B_SHIFT - HF_CS32_SHIFT);
    744                 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
    745                     new_hflags;
    746             }
    747         }
    748         new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
    749             >> (DESC_B_SHIFT - HF_SS32_SHIFT);
    750         if (env->hflags & HF_CS64_MASK) {
    751             /* zero base assumed for DS, ES and SS in long mode */
    752         } else if (!(env->cr[0] & CR0_PE_MASK) ||
    753                    (env->eflags & VM_MASK) ||
    754                    !(env->hflags & HF_CS32_MASK)) {
    755             /* XXX: try to avoid this test. The problem comes from the
    756                fact that is real mode or vm86 mode we only modify the
    757                'base' and 'selector' fields of the segment cache to go
    758                faster. A solution may be to force addseg to one in
    759                translate-i386.c. */
    760             new_hflags |= HF_ADDSEG_MASK;
    761         } else {
    762             new_hflags |= ((env->segs[R_DS].base |
    763                             env->segs[R_ES].base |
    764                             env->segs[R_SS].base) != 0) <<
    765                 HF_ADDSEG_SHIFT;
    766         }
    767         env->hflags = (env->hflags &
    768                        ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
    769     }
    770 }
    771 
    772 /* wrapper, just in case memory mappings must be changed */
    773 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
    774 {
    775 #if HF_CPL_MASK == 3
    776     s->hflags = (s->hflags & ~HF_CPL_MASK) | cpl;
    777 #else
    778 #error HF_CPL_MASK is hardcoded
    779 #endif
    780 }
    781 
    782 /* op_helper.c */
    783 /* used for debug or cpu save/restore */
    784 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, CPU86_LDouble f);
    785 CPU86_LDouble cpu_set_fp80(uint64_t mant, uint16_t upper);
    786 
    787 /* cpu-exec.c */
    788 /* the following helpers are only usable in user mode simulation as
    789    they can trigger unexpected exceptions */
    790 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
    791 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
    792 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
    793 
    794 /* you can call this signal handler from your SIGBUS and SIGSEGV
    795    signal handlers to inform the virtual CPU of exceptions. non zero
    796    is returned if the signal was handled by the virtual CPU.  */
    797 int cpu_x86_signal_handler(int host_signum, void *pinfo,
    798                            void *puc);
    799 
    800 /* helper.c */
    801 int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
    802                              int is_write, int mmu_idx, int is_softmmu);
    803 void cpu_x86_set_a20(CPUX86State *env, int a20_state);
    804 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
    805                    uint32_t *eax, uint32_t *ebx,
    806                    uint32_t *ecx, uint32_t *edx);
    807 
    808 static inline int hw_breakpoint_enabled(unsigned long dr7, int index)
    809 {
    810     return (dr7 >> (index * 2)) & 3;
    811 }
    812 
    813 static inline int hw_breakpoint_type(unsigned long dr7, int index)
    814 {
    815     return (dr7 >> (DR7_TYPE_SHIFT + (index * 2))) & 3;
    816 }
    817 
    818 static inline int hw_breakpoint_len(unsigned long dr7, int index)
    819 {
    820     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 2))) & 3);
    821     return (len == 2) ? 8 : len + 1;
    822 }
    823 
    824 void hw_breakpoint_insert(CPUX86State *env, int index);
    825 void hw_breakpoint_remove(CPUX86State *env, int index);
    826 int check_hw_breakpoints(CPUX86State *env, int force_dr6_update);
    827 
    828 /* will be suppressed */
    829 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
    830 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
    831 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
    832 
    833 /* hw/apic.c */
    834 void cpu_set_apic_base(CPUX86State *env, uint64_t val);
    835 uint64_t cpu_get_apic_base(CPUX86State *env);
    836 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
    837 #ifndef NO_CPU_IO_DEFS
    838 uint8_t cpu_get_apic_tpr(CPUX86State *env);
    839 #endif
    840 
    841 /* hw/pc.c */
    842 void cpu_smm_update(CPUX86State *env);
    843 uint64_t cpu_get_tsc(CPUX86State *env);
    844 
    845 /* used to debug */
    846 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
    847 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
    848 
    849 #ifdef CONFIG_KQEMU
    850 static inline int cpu_get_time_fast(void)
    851 {
    852     int low, high;
    853     asm volatile("rdtsc" : "=a" (low), "=d" (high));
    854     return low;
    855 }
    856 #endif
    857 
    858 #define TARGET_PAGE_BITS 12
    859 
    860 #define cpu_init cpu_x86_init
    861 #define cpu_exec cpu_x86_exec
    862 #define cpu_gen_code cpu_x86_gen_code
    863 #define cpu_signal_handler cpu_x86_signal_handler
    864 #define cpu_list x86_cpu_list
    865 
    866 #define CPU_SAVE_VERSION 10
    867 
    868 /* MMU modes definitions */
    869 #define MMU_MODE0_SUFFIX _kernel
    870 #define MMU_MODE1_SUFFIX _user
    871 #define MMU_USER_IDX 1
    872 static inline int cpu_mmu_index (CPUState *env)
    873 {
    874     return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
    875 }
    876 
    877 /* translate.c */
    878 void optimize_flags_init(void);
    879 
    880 typedef struct CCTable {
    881     int (*compute_all)(void); /* return all the flags */
    882     int (*compute_c)(void);  /* return the C flag */
    883 } CCTable;
    884 
    885 /* XXX not defined yet. Should be fixed */
    886 static inline int is_cpu_user(CPUState *env)
    887 {
    888 	return 0;
    889 }
    890 
    891 #if defined(CONFIG_USER_ONLY)
    892 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
    893 {
    894     if (newsp)
    895         env->regs[R_ESP] = newsp;
    896     env->regs[R_EAX] = 0;
    897 }
    898 #endif
    899 
    900 #include "cpu-all.h"
    901 #include "exec-all.h"
    902 
    903 #include "svm.h"
    904 
    905 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
    906 {
    907     env->eip = tb->pc - tb->cs_base;
    908 }
    909 
    910 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
    911                                         target_ulong *cs_base, int *flags)
    912 {
    913     *cs_base = env->segs[R_CS].base;
    914     *pc = *cs_base + env->eip;
    915     *flags = env->hflags |
    916         (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
    917 }
    918 
    919 void apic_init_reset(CPUState *env);
    920 void apic_sipi(CPUState *env);
    921 void do_cpu_init(CPUState *env);
    922 void do_cpu_sipi(CPUState *env);
    923 #endif /* CPU_I386_H */
    924