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    Searched defs:RA (Results 1 - 21 of 21) sorted by null

  /external/llvm/lib/Target/PowerPC/MCTargetDesc/
PPCMCTargetDesc.cpp 47 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
50 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
  /external/smack/src/org/xbill/DNS/
Flags.java 29 public static final byte RA = 8;
49 flags.add(RA, "ra");
  /external/clang/test/CodeGenCXX/
devirtualize-virtual-function-calls-final.cpp 164 struct RA {
169 struct RC final : public RA {
185 return static_cast<RA*>(x)->f();
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86MCTargetDesc.cpp 253 unsigned RA = (TheTriple.getArch() == Triple::x86_64)
258 InitX86MCRegisterInfo(X, RA,
261 RA);
  /external/llvm/lib/Target/MBlaze/Disassembler/
MBlazeDisassembler.cpp 526 unsigned RA = getRA(insn);
539 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
543 instr.addOperand(MCOperand::CreateReg(RA));
547 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
550 instr.addOperand(MCOperand::CreateReg(RA));
555 if (RD == UNSUPPORTED || RA == UNSUPPORTED)
558 instr.addOperand(MCOperand::CreateReg(RA));
572 if (RA == UNSUPPORTED)
575 instr.addOperand(MCOperand::CreateReg(RA));
588 if (RD == UNSUPPORTED || RA == UNSUPPORTED
    [all...]
  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 329 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
373 unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
378 // or $ra, $v0, $zero
380 // jr $ra
381 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), RA)
385 BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
MipsISelLowering.cpp     [all...]
  /bionic/libc/arch-mips/include/machine/
regnum.h 67 #define RA 31
  /development/ndk/platforms/android-9/arch-mips/include/machine/
regnum.h 67 #define RA 31
  /external/llvm/lib/Transforms/InstCombine/
InstCombineSimplifyDemanded.cpp 721 APInt RA = Rem->getValue().abs();
722 if (RA.isPowerOf2()) {
723 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
726 APInt LowBits = RA - 1;
    [all...]
  /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/machine/
regnum.h 67 #define RA 31
  /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/machine/
regnum.h 67 #define RA 31
  /external/llvm/lib/Analysis/
ValueTracking.cpp 548 APInt RA = Rem->getValue().abs();
549 if (RA.isPowerOf2()) {
550 APInt LowBits = RA - 1;
585 APInt RA = Rem->getValue();
586 if (RA.isPowerOf2()) {
587 APInt LowBits = (RA - 1);
    [all...]
ScalarEvolution.cpp 509 const Argument *RA = cast<Argument>(RV);
510 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo();
544 const APInt &RA = RC->getValue()->getValue();
545 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth();
548 return LA.ult(RA) ? -1 : 1;
553 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS);
556 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop();
565 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands();
571 long X = compare(LA->getOperand(i), RA->getOperand(i));
    [all...]
  /libcore/luni/src/test/java/libcore/java/util/
EnumSetTest.java 105 HF, TA, W, RE, OS, IR, PT, AU, HG, TL, PB, BI, PO, AT, RN, FR, RA, AC, TH, PA, U, NP, PU,
  /external/qemu/tcg/ppc/
tcg-target.c 397 #define RA(r) ((r)<<16)
407 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
408 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
449 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
451 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
461 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
464 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
493 tcg_out32 (s, LWZ | RT (0) | RA (reg));
494 tcg_out32 (s, MTSPR | RA (0) | CTR)
    [all...]
  /external/qemu/tcg/ppc64/
tcg-target.c 394 #define RA(r) ((r)<<16)
405 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
406 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
443 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
453 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
455 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
477 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16)
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAG.cpp     [all...]
  /external/llvm/lib/Transforms/Scalar/
LoopStrengthReduce.cpp 477 const APInt &RA = RC->getValue()->getValue();
480 if (RA.isAllOnesValue())
483 if (RA == 1)
492 const APInt &RA = RC->getValue()->getValue();
493 if (LA.srem(RA) != 0)
495 return SE.getConstant(LA.sdiv(RA));
    [all...]
  /external/qemu/
ppc-dis.c 688 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
689 #define RA NSI + 1
693 /* As above, but 0 in the RA field means zero, not r0. */
694 #define RA0 RA + 1
697 /* The RA field in the DQ form lq instruction, which has special
702 /* The RA field in a D or X form instruction which is an updating
703 load, which means that the RA field may not be zero and may not
708 /* The RA field in an lmw instruction, which has special value
713 /* The RA field in a D or X form instruction which is an updating
714 store or an updating floating point load, which means that the RA
    [all...]
  /external/robolectric/lib/main/
sqlite-jdbc-3.7.2.jar 

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