| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 458 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
478 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
483 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
552 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
557 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
560 DecodeVPR128RegisterClass(Inst, Rn, Address, Decoder);
576 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
589 // Rn_wb, Rt, Rt2, Rn, Imm
590 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
599 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn)
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 722 // [Rn, Rm]
724 // {2-0} = Rn
727 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
729 return (Rm << 3) | Rn;
744 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
824 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/qemu/ |
| arm-dis.c | 1742 int rn = (given >> 16) & 0xf; local
2071 const char *rn = arm_regnames [(given >> 16) & 0xf]; local
2284 int rn = ((given >> 16) & 0xf); local
2314 int rn = ((given >> 16) & 0xf); local
2389 int rn = ((given >> 16) & 0xf); local
[all...] |
| trace.c | 896 int Rn = (insn >> 12) & 15;
899 result += _interlock_use(Rn);
901 if (Rn != 0) /* UNDEFINED */
934 int Rn = (insn >> 16) & 15;
936 result += _interlock_use(Rn) + _interlock_use(Rm);
943 int Rn = (insn >> 16) & 15;
945 result += _interlock_use(Rn);
957 int Rn = (insn >> 16) & 15;
959 result += _interlock_use(Rn) + _interlock_use(Rm);
970 int Rn = (insn >> 16) & 15
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
