| /external/clang/lib/StaticAnalyzer/Core/ |
| SimpleConstraintManager.h | 25 SubEngine *SU;
29 : SU(subengine), BVF(BV) {}
|
| /external/llvm/lib/CodeGen/ |
| DFAPacketizer.cpp | 166 // Generate MI -> SU map.
169 SUnit *SU = &VLIWScheduler->SUnits[i];
170 MIToSUnit[SU->getInstr()] = SU;
|
| CriticalAntiDepBreaker.cpp | 124 /// CriticalPathStep - Return the next SUnit after SU on the bottom-up
126 static const SDep *CriticalPathStep(const SUnit *SU) {
130 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
424 const SUnit *SU = &SUnits[i];
425 MISUnitMap[SU->getInstr()] = SU;
426 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
427 Max = SU;
[all...] |
| ScheduleDAGInstrs.cpp | 196 /// the exit SU to the register defs and use list. This is because we want to
239 /// MO is an operand of SU's instruction that defines a physical register. Add
240 /// data dependencies from SU to any uses of the physical register.
241 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
242 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
253 SUnit *UseSU = I->SU;
254 if (UseSU == SU)
263 Dep = SDep(SU, SDep::Artificial);
265 Dep = SDep(SU, SDep::Data, *Alias);
268 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx
[all...] |
| MachineScheduler.cpp | 343 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
365 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
366 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
367 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
369 releaseSucc(SU, &*I);
377 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
399 /// releasePredecessors - Call releasePred on each of SU's predecessors.
400 void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
401 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end()
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 64 SUnit *SU = 0;
78 SU = pickAlu();
79 if (SU) {
86 if (!SU) {
88 SU = pickOther(IDFetch);
89 if (SU)
94 if (!SU) {
95 SU = pickOther(IDOther);
96 if (SU)
101 if (SU) {
[all...] |
| /external/eigen/blas/ |
| srotmg.f | 55 + SQ2,STEMP,SU,TWO,ZERO
86 SU = ONE - SH12*SH21
88 IF (.NOT.SU.LE.ZERO) GO TO 30
93 SD1 = SD1/SU
94 SD2 = SD2/SU
95 SX1 = SX1*SU
106 SU = ONE + SH11*SH22
107 STEMP = SD2/SU
108 SD2 = SD1/SU
110 SX1 = SY1*SU
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 35 SUnit *SU;
37 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
47 SUnit *SU;
51 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
153 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
154 if (!SU->SchedClass
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) {
73 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
108 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU,
111 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
146 static unsigned numberCtrlDepsInSU(SUnit *SU) {
148 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
156 static unsigned numberCtrlPredInSU(SUnit *SU) {
650 SUnit *su = q.pop(); local
[all...] |
| ScheduleDAGSDNodes.cpp | 78 SUnit *SU = &SUnits.back();
83 SU->SchedulingPref = Sched::None;
85 SU->SchedulingPref = TLI.getSchedulingPreference(N);
86 return SU;
90 SUnit *SU = newSUnit(Old->getNode());
91 SU->OrigNode = Old->OrigNode;
92 SU->Latency = Old->Latency;
93 SU->isVRegCycle = Old->isVRegCycle;
94 SU->isCall = Old->isCall;
95 SU->isCallOp = Old->isCallOp
[all...] |
| ScheduleDAGRRList.cpp | 184 /// IsReachable - Checks if SU is reachable from TargetSU.
185 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
186 return Topo.IsReachable(SU, TargetSU);
189 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
191 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
192 return Topo.WillCreateCycle(SU, TargetSU);
195 /// AddPred - adds a predecessor edge to SUnit SU.
198 void AddPred(SUnit *SU, const SDep &D) {
199 Topo.AddPred(SU, D.getSUnit());
200 SU->addPred(D)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 28 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
30 if (SUnits[su].getInstr()->isCall())
31 LastSequentialCall = &(SUnits[su]);
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall)
34 SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier));
38 /// Check if scheduling of this SU is possible
43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) {
44 if (!SU || !SU->getInstr()
[all...] |
| HexagonMachineScheduler.h | 88 bool isResourceAvailable(SUnit *SU);
89 bool reserveResources(SUnit *SU);
115 SUnit *SU;
123 SchedCandidate(): SU(NULL), SCost(0) {}
176 bool checkHazard(SUnit *SU);
178 void releaseNode(SUnit *SU, unsigned ReadyCycle);
182 void bumpNode(SUnit *SU);
186 void removeReady(SUnit *SU);
214 virtual void schedNode(SUnit *SU, bool IsTopNode);
216 virtual void releaseTopNode(SUnit *SU);
[all...] |
| HexagonVLIWPacketizer.cpp | [all...] |
| /frameworks/opt/calendar/src/com/android/calendarcommon2/ |
| EventRecurrence.java | 41 public static final int SU = 0x00010000;
55 public int wkst; // SU, MO, TU, etc.
129 sParseWeekdayMap.put("SU", SU);
164 * Converts one of the Calendar.SUNDAY constants to the SU, MO, etc.
173 return SU;
196 return SU;
217 case SU:
237 * Converts one of the SU, MO, etc. constants to the Calendar.SUNDAY
245 case SU
[all...] |
