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    Searched defs:UseIdx (Results 1 - 6 of 6) sorted by null

  /external/llvm/lib/CodeGen/
TargetSchedule.cpp 166 unsigned UseIdx = 0;
170 ++UseIdx;
172 return UseIdx;
228 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
229 return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
InlineSpiller.cpp 835 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
836 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
845 DEBUG(dbgs() << UseIdx << '\t' << *MI);
857 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
859 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
870 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
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MachineVerifier.cpp     [all...]
TwoAddressInstructionPass.cpp 369 SlotIndex useIdx = LIS->getInstructionIndex(MI);
370 LiveInterval::const_iterator I = LI.find(useIdx);
372 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
    [all...]
RegisterCoalescer.cpp 630 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI);
631 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
682 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true);
683 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
702 SlotIndex DefIdx = UseIdx.getRegSlot();
    [all...]
  /external/llvm/include/llvm/MC/
MCSchedule.h 76 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
79 unsigned UseIdx;
84 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID

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