1 //===-- PPCFrameLowering.h - Define frame lowering for PowerPC --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef POWERPC_FRAMEINFO_H 14 #define POWERPC_FRAMEINFO_H 15 16 #include "PPC.h" 17 #include "PPCSubtarget.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/Target/TargetFrameLowering.h" 20 #include "llvm/Target/TargetMachine.h" 21 22 namespace llvm { 23 class PPCSubtarget; 24 25 class PPCFrameLowering: public TargetFrameLowering { 26 const PPCSubtarget &Subtarget; 27 28 public: 29 PPCFrameLowering(const PPCSubtarget &sti) 30 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 31 (sti.hasQPX() || sti.isBGQ()) ? 32 : 16, 0), 32 Subtarget(sti) { 33 } 34 35 unsigned determineFrameLayout(MachineFunction &MF, 36 bool UpdateMF = true, 37 bool UseEstimate = false) const; 38 39 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 40 /// the function. 41 void emitPrologue(MachineFunction &MF) const; 42 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; 43 44 bool hasFP(const MachineFunction &MF) const; 45 bool needsFP(const MachineFunction &MF) const; 46 47 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 48 RegScavenger *RS = NULL) const; 49 void processFunctionBeforeFrameFinalized(MachineFunction &MF, 50 RegScavenger *RS = NULL) const; 51 void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const; 52 53 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 54 MachineBasicBlock::iterator MI, 55 const std::vector<CalleeSavedInfo> &CSI, 56 const TargetRegisterInfo *TRI) const; 57 58 void eliminateCallFramePseudoInstr(MachineFunction &MF, 59 MachineBasicBlock &MBB, 60 MachineBasicBlock::iterator I) const; 61 62 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 63 MachineBasicBlock::iterator MI, 64 const std::vector<CalleeSavedInfo> &CSI, 65 const TargetRegisterInfo *TRI) const; 66 67 /// targetHandlesStackFrameRounding - Returns true if the target is 68 /// responsible for rounding up the stack frame (probably at emitPrologue 69 /// time). 70 bool targetHandlesStackFrameRounding() const { return true; } 71 72 /// getReturnSaveOffset - Return the previous frame offset to save the 73 /// return address. 74 static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) { 75 if (isDarwinABI) 76 return isPPC64 ? 16 : 8; 77 // SVR4 ABI: 78 return isPPC64 ? 16 : 4; 79 } 80 81 /// getFramePointerSaveOffset - Return the previous frame offset to save the 82 /// frame pointer. 83 static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) { 84 // For the Darwin ABI: 85 // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area 86 // for saving the frame pointer (if needed.) While the published ABI has 87 // not used this slot since at least MacOSX 10.2, there is older code 88 // around that does use it, and that needs to continue to work. 89 if (isDarwinABI) 90 return isPPC64 ? -8U : -4U; 91 92 // SVR4 ABI: First slot in the general register save area. 93 return isPPC64 ? -8U : -4U; 94 } 95 96 /// getLinkageSize - Return the size of the PowerPC ABI linkage area. 97 /// 98 static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI) { 99 if (isDarwinABI || isPPC64) 100 return 6 * (isPPC64 ? 8 : 4); 101 102 // SVR4 ABI: 103 return 8; 104 } 105 106 /// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI 107 /// argument area. 108 static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) { 109 // For the Darwin ABI / 64-bit SVR4 ABI: 110 // The prolog code of the callee may store up to 8 GPR argument registers to 111 // the stack, allowing va_start to index over them in memory if its varargs. 112 // Because we cannot tell if this is needed on the caller side, we have to 113 // conservatively assume that it is needed. As such, make sure we have at 114 // least enough stack space for the caller to store the 8 GPRs. 115 if (isDarwinABI || isPPC64) 116 return 8 * (isPPC64 ? 8 : 4); 117 118 // 32-bit SVR4 ABI: 119 // There is no default stack allocated for the 8 first GPR arguments. 120 return 0; 121 } 122 123 /// getMinCallFrameSize - Return the minimum size a call frame can be using 124 /// the PowerPC ABI. 125 static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI) { 126 // The call frame needs to be at least big enough for linkage and 8 args. 127 return getLinkageSize(isPPC64, isDarwinABI) + 128 getMinCallArgumentsSize(isPPC64, isDarwinABI); 129 } 130 131 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. 132 const SpillSlot * 133 getCalleeSavedSpillSlots(unsigned &NumEntries) const { 134 if (Subtarget.isDarwinABI()) { 135 NumEntries = 1; 136 if (Subtarget.isPPC64()) { 137 static const SpillSlot darwin64Offsets = {PPC::X31, -8}; 138 return &darwin64Offsets; 139 } else { 140 static const SpillSlot darwinOffsets = {PPC::R31, -4}; 141 return &darwinOffsets; 142 } 143 } 144 145 // Early exit if not using the SVR4 ABI. 146 if (!Subtarget.isSVR4ABI()) { 147 NumEntries = 0; 148 return 0; 149 } 150 151 // Note that the offsets here overlap, but this is fixed up in 152 // processFunctionBeforeFrameFinalized. 153 154 static const SpillSlot Offsets[] = { 155 // Floating-point register save area offsets. 156 {PPC::F31, -8}, 157 {PPC::F30, -16}, 158 {PPC::F29, -24}, 159 {PPC::F28, -32}, 160 {PPC::F27, -40}, 161 {PPC::F26, -48}, 162 {PPC::F25, -56}, 163 {PPC::F24, -64}, 164 {PPC::F23, -72}, 165 {PPC::F22, -80}, 166 {PPC::F21, -88}, 167 {PPC::F20, -96}, 168 {PPC::F19, -104}, 169 {PPC::F18, -112}, 170 {PPC::F17, -120}, 171 {PPC::F16, -128}, 172 {PPC::F15, -136}, 173 {PPC::F14, -144}, 174 175 // General register save area offsets. 176 {PPC::R31, -4}, 177 {PPC::R30, -8}, 178 {PPC::R29, -12}, 179 {PPC::R28, -16}, 180 {PPC::R27, -20}, 181 {PPC::R26, -24}, 182 {PPC::R25, -28}, 183 {PPC::R24, -32}, 184 {PPC::R23, -36}, 185 {PPC::R22, -40}, 186 {PPC::R21, -44}, 187 {PPC::R20, -48}, 188 {PPC::R19, -52}, 189 {PPC::R18, -56}, 190 {PPC::R17, -60}, 191 {PPC::R16, -64}, 192 {PPC::R15, -68}, 193 {PPC::R14, -72}, 194 195 // CR save area offset. We map each of the nonvolatile CR fields 196 // to the slot for CR2, which is the first of the nonvolatile CR 197 // fields to be assigned, so that we only allocate one save slot. 198 // See PPCRegisterInfo::hasReservedSpillSlot() for more information. 199 {PPC::CR2, -4}, 200 201 // VRSAVE save area offset. 202 {PPC::VRSAVE, -4}, 203 204 // Vector register save area 205 {PPC::V31, -16}, 206 {PPC::V30, -32}, 207 {PPC::V29, -48}, 208 {PPC::V28, -64}, 209 {PPC::V27, -80}, 210 {PPC::V26, -96}, 211 {PPC::V25, -112}, 212 {PPC::V24, -128}, 213 {PPC::V23, -144}, 214 {PPC::V22, -160}, 215 {PPC::V21, -176}, 216 {PPC::V20, -192} 217 }; 218 219 static const SpillSlot Offsets64[] = { 220 // Floating-point register save area offsets. 221 {PPC::F31, -8}, 222 {PPC::F30, -16}, 223 {PPC::F29, -24}, 224 {PPC::F28, -32}, 225 {PPC::F27, -40}, 226 {PPC::F26, -48}, 227 {PPC::F25, -56}, 228 {PPC::F24, -64}, 229 {PPC::F23, -72}, 230 {PPC::F22, -80}, 231 {PPC::F21, -88}, 232 {PPC::F20, -96}, 233 {PPC::F19, -104}, 234 {PPC::F18, -112}, 235 {PPC::F17, -120}, 236 {PPC::F16, -128}, 237 {PPC::F15, -136}, 238 {PPC::F14, -144}, 239 240 // General register save area offsets. 241 {PPC::X31, -8}, 242 {PPC::X30, -16}, 243 {PPC::X29, -24}, 244 {PPC::X28, -32}, 245 {PPC::X27, -40}, 246 {PPC::X26, -48}, 247 {PPC::X25, -56}, 248 {PPC::X24, -64}, 249 {PPC::X23, -72}, 250 {PPC::X22, -80}, 251 {PPC::X21, -88}, 252 {PPC::X20, -96}, 253 {PPC::X19, -104}, 254 {PPC::X18, -112}, 255 {PPC::X17, -120}, 256 {PPC::X16, -128}, 257 {PPC::X15, -136}, 258 {PPC::X14, -144}, 259 260 // VRSAVE save area offset. 261 {PPC::VRSAVE, -4}, 262 263 // Vector register save area 264 {PPC::V31, -16}, 265 {PPC::V30, -32}, 266 {PPC::V29, -48}, 267 {PPC::V28, -64}, 268 {PPC::V27, -80}, 269 {PPC::V26, -96}, 270 {PPC::V25, -112}, 271 {PPC::V24, -128}, 272 {PPC::V23, -144}, 273 {PPC::V22, -160}, 274 {PPC::V21, -176}, 275 {PPC::V20, -192} 276 }; 277 278 if (Subtarget.isPPC64()) { 279 NumEntries = array_lengthof(Offsets64); 280 281 return Offsets64; 282 } else { 283 NumEntries = array_lengthof(Offsets); 284 285 return Offsets; 286 } 287 } 288 }; 289 290 } // End llvm namespace 291 292 #endif 293
