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      1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the LiveVariable analysis pass.  For each machine
     11 // instruction in the function, this pass calculates the set of registers that
     12 // are immediately dead after the instruction (i.e., the instruction calculates
     13 // the value, but it is never used) and the set of registers that are used by
     14 // the instruction, but are never used after the instruction (i.e., they are
     15 // killed).
     16 //
     17 // This class computes live variables using a sparse implementation based on
     18 // the machine code SSA form.  This class computes live variable information for
     19 // each virtual and _register allocatable_ physical register in a function.  It
     20 // uses the dominance properties of SSA form to efficiently compute live
     21 // variables for virtual registers, and assumes that physical registers are only
     22 // live within a single basic block (allowing it to do a single local analysis
     23 // to resolve physical register lifetimes in each basic block).  If a physical
     24 // register is not register allocatable, it is not tracked.  This is useful for
     25 // things like the stack pointer and condition codes.
     26 //
     27 //===----------------------------------------------------------------------===//
     28 
     29 #include "llvm/CodeGen/LiveVariables.h"
     30 #include "llvm/ADT/DepthFirstIterator.h"
     31 #include "llvm/ADT/STLExtras.h"
     32 #include "llvm/ADT/SmallPtrSet.h"
     33 #include "llvm/ADT/SmallSet.h"
     34 #include "llvm/CodeGen/MachineInstr.h"
     35 #include "llvm/CodeGen/MachineRegisterInfo.h"
     36 #include "llvm/CodeGen/Passes.h"
     37 #include "llvm/Support/Debug.h"
     38 #include "llvm/Support/ErrorHandling.h"
     39 #include "llvm/Target/TargetInstrInfo.h"
     40 #include "llvm/Target/TargetMachine.h"
     41 #include <algorithm>
     42 using namespace llvm;
     43 
     44 char LiveVariables::ID = 0;
     45 char &llvm::LiveVariablesID = LiveVariables::ID;
     46 INITIALIZE_PASS_BEGIN(LiveVariables, "livevars",
     47                 "Live Variable Analysis", false, false)
     48 INITIALIZE_PASS_DEPENDENCY(UnreachableMachineBlockElim)
     49 INITIALIZE_PASS_END(LiveVariables, "livevars",
     50                 "Live Variable Analysis", false, false)
     51 
     52 
     53 void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
     54   AU.addRequiredID(UnreachableMachineBlockElimID);
     55   AU.setPreservesAll();
     56   MachineFunctionPass::getAnalysisUsage(AU);
     57 }
     58 
     59 MachineInstr *
     60 LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
     61   for (unsigned i = 0, e = Kills.size(); i != e; ++i)
     62     if (Kills[i]->getParent() == MBB)
     63       return Kills[i];
     64   return NULL;
     65 }
     66 
     67 void LiveVariables::VarInfo::dump() const {
     68 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     69   dbgs() << "  Alive in blocks: ";
     70   for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
     71            E = AliveBlocks.end(); I != E; ++I)
     72     dbgs() << *I << ", ";
     73   dbgs() << "\n  Killed by:";
     74   if (Kills.empty())
     75     dbgs() << " No instructions.\n";
     76   else {
     77     for (unsigned i = 0, e = Kills.size(); i != e; ++i)
     78       dbgs() << "\n    #" << i << ": " << *Kills[i];
     79     dbgs() << "\n";
     80   }
     81 #endif
     82 }
     83 
     84 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
     85 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
     86   assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
     87          "getVarInfo: not a virtual register!");
     88   VirtRegInfo.grow(RegIdx);
     89   return VirtRegInfo[RegIdx];
     90 }
     91 
     92 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
     93                                             MachineBasicBlock *DefBlock,
     94                                             MachineBasicBlock *MBB,
     95                                     std::vector<MachineBasicBlock*> &WorkList) {
     96   unsigned BBNum = MBB->getNumber();
     97 
     98   // Check to see if this basic block is one of the killing blocks.  If so,
     99   // remove it.
    100   for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
    101     if (VRInfo.Kills[i]->getParent() == MBB) {
    102       VRInfo.Kills.erase(VRInfo.Kills.begin()+i);  // Erase entry
    103       break;
    104     }
    105 
    106   if (MBB == DefBlock) return;  // Terminate recursion
    107 
    108   if (VRInfo.AliveBlocks.test(BBNum))
    109     return;  // We already know the block is live
    110 
    111   // Mark the variable known alive in this bb
    112   VRInfo.AliveBlocks.set(BBNum);
    113 
    114   assert(MBB != &MF->front() && "Can't find reaching def for virtreg");
    115   WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());
    116 }
    117 
    118 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
    119                                             MachineBasicBlock *DefBlock,
    120                                             MachineBasicBlock *MBB) {
    121   std::vector<MachineBasicBlock*> WorkList;
    122   MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
    123 
    124   while (!WorkList.empty()) {
    125     MachineBasicBlock *Pred = WorkList.back();
    126     WorkList.pop_back();
    127     MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
    128   }
    129 }
    130 
    131 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
    132                                      MachineInstr *MI) {
    133   assert(MRI->getVRegDef(reg) && "Register use before def!");
    134 
    135   unsigned BBNum = MBB->getNumber();
    136 
    137   VarInfo& VRInfo = getVarInfo(reg);
    138 
    139   // Check to see if this basic block is already a kill block.
    140   if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
    141     // Yes, this register is killed in this basic block already. Increase the
    142     // live range by updating the kill instruction.
    143     VRInfo.Kills.back() = MI;
    144     return;
    145   }
    146 
    147 #ifndef NDEBUG
    148   for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
    149     assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
    150 #endif
    151 
    152   // This situation can occur:
    153   //
    154   //     ,------.
    155   //     |      |
    156   //     |      v
    157   //     |   t2 = phi ... t1 ...
    158   //     |      |
    159   //     |      v
    160   //     |   t1 = ...
    161   //     |  ... = ... t1 ...
    162   //     |      |
    163   //     `------'
    164   //
    165   // where there is a use in a PHI node that's a predecessor to the defining
    166   // block. We don't want to mark all predecessors as having the value "alive"
    167   // in this case.
    168   if (MBB == MRI->getVRegDef(reg)->getParent()) return;
    169 
    170   // Add a new kill entry for this basic block. If this virtual register is
    171   // already marked as alive in this basic block, that means it is alive in at
    172   // least one of the successor blocks, it's not a kill.
    173   if (!VRInfo.AliveBlocks.test(BBNum))
    174     VRInfo.Kills.push_back(MI);
    175 
    176   // Update all dominating blocks to mark them as "known live".
    177   for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
    178          E = MBB->pred_end(); PI != E; ++PI)
    179     MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
    180 }
    181 
    182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
    183   VarInfo &VRInfo = getVarInfo(Reg);
    184 
    185   if (VRInfo.AliveBlocks.empty())
    186     // If vr is not alive in any block, then defaults to dead.
    187     VRInfo.Kills.push_back(MI);
    188 }
    189 
    190 /// FindLastPartialDef - Return the last partial def of the specified register.
    191 /// Also returns the sub-registers that're defined by the instruction.
    192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
    193                                             SmallSet<unsigned,4> &PartDefRegs) {
    194   unsigned LastDefReg = 0;
    195   unsigned LastDefDist = 0;
    196   MachineInstr *LastDef = NULL;
    197   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
    198     unsigned SubReg = *SubRegs;
    199     MachineInstr *Def = PhysRegDef[SubReg];
    200     if (!Def)
    201       continue;
    202     unsigned Dist = DistanceMap[Def];
    203     if (Dist > LastDefDist) {
    204       LastDefReg  = SubReg;
    205       LastDef     = Def;
    206       LastDefDist = Dist;
    207     }
    208   }
    209 
    210   if (!LastDef)
    211     return 0;
    212 
    213   PartDefRegs.insert(LastDefReg);
    214   for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
    215     MachineOperand &MO = LastDef->getOperand(i);
    216     if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
    217       continue;
    218     unsigned DefReg = MO.getReg();
    219     if (TRI->isSubRegister(Reg, DefReg)) {
    220       PartDefRegs.insert(DefReg);
    221       for (MCSubRegIterator SubRegs(DefReg, TRI); SubRegs.isValid(); ++SubRegs)
    222         PartDefRegs.insert(*SubRegs);
    223     }
    224   }
    225   return LastDef;
    226 }
    227 
    228 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
    229 /// implicit defs to a machine instruction if there was an earlier def of its
    230 /// super-register.
    231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
    232   MachineInstr *LastDef = PhysRegDef[Reg];
    233   // If there was a previous use or a "full" def all is well.
    234   if (!LastDef && !PhysRegUse[Reg]) {
    235     // Otherwise, the last sub-register def implicitly defines this register.
    236     // e.g.
    237     // AH =
    238     // AL = ... <imp-def EAX>, <imp-kill AH>
    239     //    = AH
    240     // ...
    241     //    = EAX
    242     // All of the sub-registers must have been defined before the use of Reg!
    243     SmallSet<unsigned, 4> PartDefRegs;
    244     MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
    245     // If LastPartialDef is NULL, it must be using a livein register.
    246     if (LastPartialDef) {
    247       LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
    248                                                            true/*IsImp*/));
    249       PhysRegDef[Reg] = LastPartialDef;
    250       SmallSet<unsigned, 8> Processed;
    251       for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
    252         unsigned SubReg = *SubRegs;
    253         if (Processed.count(SubReg))
    254           continue;
    255         if (PartDefRegs.count(SubReg))
    256           continue;
    257         // This part of Reg was defined before the last partial def. It's killed
    258         // here.
    259         LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
    260                                                              false/*IsDef*/,
    261                                                              true/*IsImp*/));
    262         PhysRegDef[SubReg] = LastPartialDef;
    263         for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
    264           Processed.insert(*SS);
    265       }
    266     }
    267   } else if (LastDef && !PhysRegUse[Reg] &&
    268              !LastDef->findRegisterDefOperand(Reg))
    269     // Last def defines the super register, add an implicit def of reg.
    270     LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
    271                                                   true/*IsImp*/));
    272 
    273   // Remember this use.
    274   PhysRegUse[Reg]  = MI;
    275   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
    276     PhysRegUse[*SubRegs] =  MI;
    277 }
    278 
    279 /// FindLastRefOrPartRef - Return the last reference or partial reference of
    280 /// the specified register.
    281 MachineInstr *LiveVariables::FindLastRefOrPartRef(unsigned Reg) {
    282   MachineInstr *LastDef = PhysRegDef[Reg];
    283   MachineInstr *LastUse = PhysRegUse[Reg];
    284   if (!LastDef && !LastUse)
    285     return 0;
    286 
    287   MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
    288   unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
    289   unsigned LastPartDefDist = 0;
    290   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
    291     unsigned SubReg = *SubRegs;
    292     MachineInstr *Def = PhysRegDef[SubReg];
    293     if (Def && Def != LastDef) {
    294       // There was a def of this sub-register in between. This is a partial
    295       // def, keep track of the last one.
    296       unsigned Dist = DistanceMap[Def];
    297       if (Dist > LastPartDefDist)
    298         LastPartDefDist = Dist;
    299     } else if (MachineInstr *Use = PhysRegUse[SubReg]) {
    300       unsigned Dist = DistanceMap[Use];
    301       if (Dist > LastRefOrPartRefDist) {
    302         LastRefOrPartRefDist = Dist;
    303         LastRefOrPartRef = Use;
    304       }
    305     }
    306   }
    307 
    308   return LastRefOrPartRef;
    309 }
    310 
    311 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
    312   MachineInstr *LastDef = PhysRegDef[Reg];
    313   MachineInstr *LastUse = PhysRegUse[Reg];
    314   if (!LastDef && !LastUse)
    315     return false;
    316 
    317   MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
    318   unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
    319   // The whole register is used.
    320   // AL =
    321   // AH =
    322   //
    323   //    = AX
    324   //    = AL, AX<imp-use, kill>
    325   // AX =
    326   //
    327   // Or whole register is defined, but not used at all.
    328   // AX<dead> =
    329   // ...
    330   // AX =
    331   //
    332   // Or whole register is defined, but only partly used.
    333   // AX<dead> = AL<imp-def>
    334   //    = AL<kill>
    335   // AX =
    336   MachineInstr *LastPartDef = 0;
    337   unsigned LastPartDefDist = 0;
    338   SmallSet<unsigned, 8> PartUses;
    339   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
    340     unsigned SubReg = *SubRegs;
    341     MachineInstr *Def = PhysRegDef[SubReg];
    342     if (Def && Def != LastDef) {
    343       // There was a def of this sub-register in between. This is a partial
    344       // def, keep track of the last one.
    345       unsigned Dist = DistanceMap[Def];
    346       if (Dist > LastPartDefDist) {
    347         LastPartDefDist = Dist;
    348         LastPartDef = Def;
    349       }
    350       continue;
    351     }
    352     if (MachineInstr *Use = PhysRegUse[SubReg]) {
    353       PartUses.insert(SubReg);
    354       for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
    355         PartUses.insert(*SS);
    356       unsigned Dist = DistanceMap[Use];
    357       if (Dist > LastRefOrPartRefDist) {
    358         LastRefOrPartRefDist = Dist;
    359         LastRefOrPartRef = Use;
    360       }
    361     }
    362   }
    363 
    364   if (!PhysRegUse[Reg]) {
    365     // Partial uses. Mark register def dead and add implicit def of
    366     // sub-registers which are used.
    367     // EAX<dead>  = op  AL<imp-def>
    368     // That is, EAX def is dead but AL def extends pass it.
    369     PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
    370     for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
    371       unsigned SubReg = *SubRegs;
    372       if (!PartUses.count(SubReg))
    373         continue;
    374       bool NeedDef = true;
    375       if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
    376         MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
    377         if (MO) {
    378           NeedDef = false;
    379           assert(!MO->isDead());
    380         }
    381       }
    382       if (NeedDef)
    383         PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
    384                                                  true/*IsDef*/, true/*IsImp*/));
    385       MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
    386       if (LastSubRef)
    387         LastSubRef->addRegisterKilled(SubReg, TRI, true);
    388       else {
    389         LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
    390         PhysRegUse[SubReg] = LastRefOrPartRef;
    391         for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
    392           PhysRegUse[*SS] = LastRefOrPartRef;
    393       }
    394       for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
    395         PartUses.erase(*SS);
    396     }
    397   } else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
    398     if (LastPartDef)
    399       // The last partial def kills the register.
    400       LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
    401                                                 true/*IsImp*/, true/*IsKill*/));
    402     else {
    403       MachineOperand *MO =
    404         LastRefOrPartRef->findRegisterDefOperand(Reg, false, TRI);
    405       bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
    406       // If the last reference is the last def, then it's not used at all.
    407       // That is, unless we are currently processing the last reference itself.
    408       LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
    409       if (NeedEC) {
    410         // If we are adding a subreg def and the superreg def is marked early
    411         // clobber, add an early clobber marker to the subreg def.
    412         MO = LastRefOrPartRef->findRegisterDefOperand(Reg);
    413         if (MO)
    414           MO->setIsEarlyClobber();
    415       }
    416     }
    417   } else
    418     LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
    419   return true;
    420 }
    421 
    422 void LiveVariables::HandleRegMask(const MachineOperand &MO) {
    423   // Call HandlePhysRegKill() for all live registers clobbered by Mask.
    424   // Clobbered registers are always dead, sp there is no need to use
    425   // HandlePhysRegDef().
    426   for (unsigned Reg = 1, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg) {
    427     // Skip dead regs.
    428     if (!PhysRegDef[Reg] && !PhysRegUse[Reg])
    429       continue;
    430     // Skip mask-preserved regs.
    431     if (!MO.clobbersPhysReg(Reg))
    432       continue;
    433     // Kill the largest clobbered super-register.
    434     // This avoids needless implicit operands.
    435     unsigned Super = Reg;
    436     for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
    437       if ((PhysRegDef[*SR] || PhysRegUse[*SR]) && MO.clobbersPhysReg(*SR))
    438         Super = *SR;
    439     HandlePhysRegKill(Super, 0);
    440   }
    441 }
    442 
    443 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
    444                                      SmallVector<unsigned, 4> &Defs) {
    445   // What parts of the register are previously defined?
    446   SmallSet<unsigned, 32> Live;
    447   if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
    448     Live.insert(Reg);
    449     for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
    450       Live.insert(*SubRegs);
    451   } else {
    452     for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
    453       unsigned SubReg = *SubRegs;
    454       // If a register isn't itself defined, but all parts that make up of it
    455       // are defined, then consider it also defined.
    456       // e.g.
    457       // AL =
    458       // AH =
    459       //    = AX
    460       if (Live.count(SubReg))
    461         continue;
    462       if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
    463         Live.insert(SubReg);
    464         for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
    465           Live.insert(*SS);
    466       }
    467     }
    468   }
    469 
    470   // Start from the largest piece, find the last time any part of the register
    471   // is referenced.
    472   HandlePhysRegKill(Reg, MI);
    473   // Only some of the sub-registers are used.
    474   for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
    475     unsigned SubReg = *SubRegs;
    476     if (!Live.count(SubReg))
    477       // Skip if this sub-register isn't defined.
    478       continue;
    479     HandlePhysRegKill(SubReg, MI);
    480   }
    481 
    482   if (MI)
    483     Defs.push_back(Reg);  // Remember this def.
    484 }
    485 
    486 void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
    487                                       SmallVector<unsigned, 4> &Defs) {
    488   while (!Defs.empty()) {
    489     unsigned Reg = Defs.back();
    490     Defs.pop_back();
    491     PhysRegDef[Reg]  = MI;
    492     PhysRegUse[Reg]  = NULL;
    493     for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
    494       unsigned SubReg = *SubRegs;
    495       PhysRegDef[SubReg]  = MI;
    496       PhysRegUse[SubReg]  = NULL;
    497     }
    498   }
    499 }
    500 
    501 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
    502   MF = &mf;
    503   MRI = &mf.getRegInfo();
    504   TRI = MF->getTarget().getRegisterInfo();
    505 
    506   unsigned NumRegs = TRI->getNumRegs();
    507   PhysRegDef  = new MachineInstr*[NumRegs];
    508   PhysRegUse  = new MachineInstr*[NumRegs];
    509   PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
    510   std::fill(PhysRegDef,  PhysRegDef  + NumRegs, (MachineInstr*)0);
    511   std::fill(PhysRegUse,  PhysRegUse  + NumRegs, (MachineInstr*)0);
    512   PHIJoins.clear();
    513 
    514   // FIXME: LiveIntervals will be updated to remove its dependence on
    515   // LiveVariables to improve compilation time and eliminate bizarre pass
    516   // dependencies. Until then, we can't change much in -O0.
    517   if (!MRI->isSSA())
    518     report_fatal_error("regalloc=... not currently supported with -O0");
    519 
    520   analyzePHINodes(mf);
    521 
    522   // Calculate live variable information in depth first order on the CFG of the
    523   // function.  This guarantees that we will see the definition of a virtual
    524   // register before its uses due to dominance properties of SSA (except for PHI
    525   // nodes, which are treated as a special case).
    526   MachineBasicBlock *Entry = MF->begin();
    527   SmallPtrSet<MachineBasicBlock*,16> Visited;
    528 
    529   for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
    530          DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
    531        DFI != E; ++DFI) {
    532     MachineBasicBlock *MBB = *DFI;
    533 
    534     // Mark live-in registers as live-in.
    535     SmallVector<unsigned, 4> Defs;
    536     for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
    537            EE = MBB->livein_end(); II != EE; ++II) {
    538       assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
    539              "Cannot have a live-in virtual register!");
    540       HandlePhysRegDef(*II, 0, Defs);
    541     }
    542 
    543     // Loop over all of the instructions, processing them.
    544     DistanceMap.clear();
    545     unsigned Dist = 0;
    546     for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
    547          I != E; ++I) {
    548       MachineInstr *MI = I;
    549       if (MI->isDebugValue())
    550         continue;
    551       DistanceMap.insert(std::make_pair(MI, Dist++));
    552 
    553       // Process all of the operands of the instruction...
    554       unsigned NumOperandsToProcess = MI->getNumOperands();
    555 
    556       // Unless it is a PHI node.  In this case, ONLY process the DEF, not any
    557       // of the uses.  They will be handled in other basic blocks.
    558       if (MI->isPHI())
    559         NumOperandsToProcess = 1;
    560 
    561       // Clear kill and dead markers. LV will recompute them.
    562       SmallVector<unsigned, 4> UseRegs;
    563       SmallVector<unsigned, 4> DefRegs;
    564       SmallVector<unsigned, 1> RegMasks;
    565       for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
    566         MachineOperand &MO = MI->getOperand(i);
    567         if (MO.isRegMask()) {
    568           RegMasks.push_back(i);
    569           continue;
    570         }
    571         if (!MO.isReg() || MO.getReg() == 0)
    572           continue;
    573         unsigned MOReg = MO.getReg();
    574         if (MO.isUse()) {
    575           MO.setIsKill(false);
    576           if (MO.readsReg())
    577             UseRegs.push_back(MOReg);
    578         } else /*MO.isDef()*/ {
    579           MO.setIsDead(false);
    580           DefRegs.push_back(MOReg);
    581         }
    582       }
    583 
    584       // Process all uses.
    585       for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
    586         unsigned MOReg = UseRegs[i];
    587         if (TargetRegisterInfo::isVirtualRegister(MOReg))
    588           HandleVirtRegUse(MOReg, MBB, MI);
    589         else if (!MRI->isReserved(MOReg))
    590           HandlePhysRegUse(MOReg, MI);
    591       }
    592 
    593       // Process all masked registers. (Call clobbers).
    594       for (unsigned i = 0, e = RegMasks.size(); i != e; ++i)
    595         HandleRegMask(MI->getOperand(RegMasks[i]));
    596 
    597       // Process all defs.
    598       for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
    599         unsigned MOReg = DefRegs[i];
    600         if (TargetRegisterInfo::isVirtualRegister(MOReg))
    601           HandleVirtRegDef(MOReg, MI);
    602         else if (!MRI->isReserved(MOReg))
    603           HandlePhysRegDef(MOReg, MI, Defs);
    604       }
    605       UpdatePhysRegDefs(MI, Defs);
    606     }
    607 
    608     // Handle any virtual assignments from PHI nodes which might be at the
    609     // bottom of this basic block.  We check all of our successor blocks to see
    610     // if they have PHI nodes, and if so, we simulate an assignment at the end
    611     // of the current block.
    612     if (!PHIVarInfo[MBB->getNumber()].empty()) {
    613       SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
    614 
    615       for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
    616              E = VarInfoVec.end(); I != E; ++I)
    617         // Mark it alive only in the block we are representing.
    618         MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
    619                                 MBB);
    620     }
    621 
    622     // MachineCSE may CSE instructions which write to non-allocatable physical
    623     // registers across MBBs. Remember if any reserved register is liveout.
    624     SmallSet<unsigned, 4> LiveOuts;
    625     for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
    626            SE = MBB->succ_end(); SI != SE; ++SI) {
    627       MachineBasicBlock *SuccMBB = *SI;
    628       if (SuccMBB->isLandingPad())
    629         continue;
    630       for (MachineBasicBlock::livein_iterator LI = SuccMBB->livein_begin(),
    631              LE = SuccMBB->livein_end(); LI != LE; ++LI) {
    632         unsigned LReg = *LI;
    633         if (!TRI->isInAllocatableClass(LReg))
    634           // Ignore other live-ins, e.g. those that are live into landing pads.
    635           LiveOuts.insert(LReg);
    636       }
    637     }
    638 
    639     // Loop over PhysRegDef / PhysRegUse, killing any registers that are
    640     // available at the end of the basic block.
    641     for (unsigned i = 0; i != NumRegs; ++i)
    642       if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(i))
    643         HandlePhysRegDef(i, 0, Defs);
    644 
    645     std::fill(PhysRegDef,  PhysRegDef  + NumRegs, (MachineInstr*)0);
    646     std::fill(PhysRegUse,  PhysRegUse  + NumRegs, (MachineInstr*)0);
    647   }
    648 
    649   // Convert and transfer the dead / killed information we have gathered into
    650   // VirtRegInfo onto MI's.
    651   for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
    652     const unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
    653     for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
    654       if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
    655         VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
    656       else
    657         VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
    658   }
    659 
    660   // Check to make sure there are no unreachable blocks in the MC CFG for the
    661   // function.  If so, it is due to a bug in the instruction selector or some
    662   // other part of the code generator if this happens.
    663 #ifndef NDEBUG
    664   for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
    665     assert(Visited.count(&*i) != 0 && "unreachable basic block found");
    666 #endif
    667 
    668   delete[] PhysRegDef;
    669   delete[] PhysRegUse;
    670   delete[] PHIVarInfo;
    671 
    672   return false;
    673 }
    674 
    675 /// replaceKillInstruction - Update register kill info by replacing a kill
    676 /// instruction with a new one.
    677 void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
    678                                            MachineInstr *NewMI) {
    679   VarInfo &VI = getVarInfo(Reg);
    680   std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
    681 }
    682 
    683 /// removeVirtualRegistersKilled - Remove all killed info for the specified
    684 /// instruction.
    685 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
    686   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    687     MachineOperand &MO = MI->getOperand(i);
    688     if (MO.isReg() && MO.isKill()) {
    689       MO.setIsKill(false);
    690       unsigned Reg = MO.getReg();
    691       if (TargetRegisterInfo::isVirtualRegister(Reg)) {
    692         bool removed = getVarInfo(Reg).removeKill(MI);
    693         assert(removed && "kill not in register's VarInfo?");
    694         (void)removed;
    695       }
    696     }
    697   }
    698 }
    699 
    700 /// analyzePHINodes - Gather information about the PHI nodes in here. In
    701 /// particular, we want to map the variable information of a virtual register
    702 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
    703 ///
    704 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
    705   for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
    706        I != E; ++I)
    707     for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
    708          BBI != BBE && BBI->isPHI(); ++BBI)
    709       for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
    710         if (BBI->getOperand(i).readsReg())
    711           PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
    712             .push_back(BBI->getOperand(i).getReg());
    713 }
    714 
    715 bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
    716                                       unsigned Reg,
    717                                       MachineRegisterInfo &MRI) {
    718   unsigned Num = MBB.getNumber();
    719 
    720   // Reg is live-through.
    721   if (AliveBlocks.test(Num))
    722     return true;
    723 
    724   // Registers defined in MBB cannot be live in.
    725   const MachineInstr *Def = MRI.getVRegDef(Reg);
    726   if (Def && Def->getParent() == &MBB)
    727     return false;
    728 
    729  // Reg was not defined in MBB, was it killed here?
    730   return findKill(&MBB);
    731 }
    732 
    733 bool LiveVariables::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) {
    734   LiveVariables::VarInfo &VI = getVarInfo(Reg);
    735 
    736   // Loop over all of the successors of the basic block, checking to see if
    737   // the value is either live in the block, or if it is killed in the block.
    738   SmallVector<MachineBasicBlock*, 8> OpSuccBlocks;
    739   for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
    740          E = MBB.succ_end(); SI != E; ++SI) {
    741     MachineBasicBlock *SuccMBB = *SI;
    742 
    743     // Is it alive in this successor?
    744     unsigned SuccIdx = SuccMBB->getNumber();
    745     if (VI.AliveBlocks.test(SuccIdx))
    746       return true;
    747     OpSuccBlocks.push_back(SuccMBB);
    748   }
    749 
    750   // Check to see if this value is live because there is a use in a successor
    751   // that kills it.
    752   switch (OpSuccBlocks.size()) {
    753   case 1: {
    754     MachineBasicBlock *SuccMBB = OpSuccBlocks[0];
    755     for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
    756       if (VI.Kills[i]->getParent() == SuccMBB)
    757         return true;
    758     break;
    759   }
    760   case 2: {
    761     MachineBasicBlock *SuccMBB1 = OpSuccBlocks[0], *SuccMBB2 = OpSuccBlocks[1];
    762     for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
    763       if (VI.Kills[i]->getParent() == SuccMBB1 ||
    764           VI.Kills[i]->getParent() == SuccMBB2)
    765         return true;
    766     break;
    767   }
    768   default:
    769     std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end());
    770     for (unsigned i = 0, e = VI.Kills.size(); i != e; ++i)
    771       if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(),
    772                              VI.Kills[i]->getParent()))
    773         return true;
    774   }
    775   return false;
    776 }
    777 
    778 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
    779 /// variables that are live out of DomBB will be marked as passing live through
    780 /// BB.
    781 void LiveVariables::addNewBlock(MachineBasicBlock *BB,
    782                                 MachineBasicBlock *DomBB,
    783                                 MachineBasicBlock *SuccBB) {
    784   const unsigned NumNew = BB->getNumber();
    785 
    786   SmallSet<unsigned, 16> Defs, Kills;
    787 
    788   MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end();
    789   for (; BBI != BBE && BBI->isPHI(); ++BBI) {
    790     // Record the def of the PHI node.
    791     Defs.insert(BBI->getOperand(0).getReg());
    792 
    793     // All registers used by PHI nodes in SuccBB must be live through BB.
    794     for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
    795       if (BBI->getOperand(i+1).getMBB() == BB)
    796         getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
    797   }
    798 
    799   // Record all vreg defs and kills of all instructions in SuccBB.
    800   for (; BBI != BBE; ++BBI) {
    801     for (MachineInstr::mop_iterator I = BBI->operands_begin(),
    802          E = BBI->operands_end(); I != E; ++I) {
    803       if (I->isReg() && TargetRegisterInfo::isVirtualRegister(I->getReg())) {
    804         if (I->isDef())
    805           Defs.insert(I->getReg());
    806         else if (I->isKill())
    807           Kills.insert(I->getReg());
    808       }
    809     }
    810   }
    811 
    812   // Update info for all live variables
    813   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
    814     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
    815 
    816     // If the Defs is defined in the successor it can't be live in BB.
    817     if (Defs.count(Reg))
    818       continue;
    819 
    820     // If the register is either killed in or live through SuccBB it's also live
    821     // through BB.
    822     VarInfo &VI = getVarInfo(Reg);
    823     if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))
    824       VI.AliveBlocks.set(NumNew);
    825   }
    826 }
    827