| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 657 bool isTailCall = (RetOpcode == ARM::TCRETURNdi ||
673 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) {
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 391 bool &isTailCall = CLI.IsTailCall;
426 if(isTailCall) {
429 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
436 isTailCall = false;
440 if (isTailCall) {
514 if (!isTailCall)
523 if (!isTailCall) {
532 if (isTailCall) {
583 if (isTailCall)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 684 /// TODO: isVarArg, isTailCall.
695 bool &isTailCall = CLI.IsTailCall;
700 isTailCall = false;
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 285 bool &isTailCall = CLI.IsTailCall;
290 isTailCall = false;
297 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
461 bool isTailCall,
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 354 bool &isTailCall = CLI.IsTailCall;
359 isTailCall = false;
[all...] |
| /external/llvm/include/llvm/IR/ |
| Instructions.h | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 420 bool &isTailCall = CLI.IsTailCall;
786 // set isTailCall to false for now, until we figure out how to express
788 isTailCall = false;
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 490 false, false, 0, CallingConv::C, /*isTailCall=*/false,
553 false, false, 0, CallingConv::C, /*isTailCall=*/false,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
